Commit Graph

19054 Commits

Author SHA1 Message Date
Jeffrey Yasskin
a44defeb22 Explicitly cast narrowing conversions inside {}s that will become errors in
C++0x.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 06:22:51 +00:00
Bruno Cardoso Lopes
9b4ad12b1e Move some code around to open opportunity for more shuffle matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:56:37 +00:00
Bruno Cardoso Lopes
cea34e41fa The vpermilps and vpermilpd have different behaviour regarding the
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:56:34 +00:00
Bruno Cardoso Lopes
cd9e5aed53 Remove more dead code!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:56:27 +00:00
Evan Cheng
bd27f5adbd Support .code32 and .code64 in X86 assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:38:12 +00:00
Benjamin Kramer
162ee5c725 Add a neat little two's complement hack for x86.
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 22:42:13 +00:00
Bruno Cardoso Lopes
4ea496846a Recognize unpckh* masks and match 256-bit versions. The new versions are
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 22:03:40 +00:00
Jim Grosbach
45f3929ef0 ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:44:37 +00:00
Jim Grosbach
85bfd3b023 ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:28:43 +00:00
Eli Friedman
61cc47e15d Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:02:58 +00:00
Owen Anderson
793e79601f Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:54:26 +00:00
Nicolas Geoffray
45c8d2bc9c Update generated code to use new API of GetElementPtrInst::Create.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136138 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:52:25 +00:00
Jim Grosbach
0d87ec21d7 Fix over-zealous rename from r136095.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:41:24 +00:00
Jim Grosbach
189610f946 ARM diagnostics for ldrexd/stredx out of order paired register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:25:39 +00:00
Bruno Cardoso Lopes
cf128eab90 Remove now unused patterns. 0 insertions(+), 98 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:22:39 +00:00
Bruno Cardoso Lopes
5e3267dac9 Cleanup old matching for PUNPCK* variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:22:27 +00:00
Jim Grosbach
dfdf02dbad ARM fix for LDREX source register encoding.
rdar://9842203


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:44:46 +00:00
Jim Grosbach
4f6f13db1a ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:15:11 +00:00
Jim Grosbach
1ef91417bd ARM SWP instructions store, too, not just load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:11:05 +00:00
Jim Grosbach
1355cf1f76 Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:10:22 +00:00
Jim Grosbach
3d5ab367b6 ARM fix asm parsing range check for [0,31] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 16:44:05 +00:00
Jim Grosbach
ed8384806e ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 16:24:27 +00:00
Bill Wendling
de77055a68 The compact unwinding offsets are divided by 8 on 64-bit machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 08:03:49 +00:00
Bruno Cardoso Lopes
5d348b4dc4 Add 256-bit isel for movsldup/movshdup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:32 +00:00
Bruno Cardoso Lopes
9123c6fea0 More movsldup/movshdup cleanup. Rewrite the mask matching function and add
support for 256-bit versions (but no instruction selection yet, coming next).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:28 +00:00
Bruno Cardoso Lopes
5f6c440e53 More cleanup, subtarget info isn't used here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:25 +00:00
Bruno Cardoso Lopes
cc1c3526a7 Add 128-bit AVX versions of movshdup/mosldup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:23 +00:00
Bruno Cardoso Lopes
3e9235c720 Cleanup movsldup/movshdup matching.
27 insertions(+), 62 deletions(-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:13 +00:00
Evan Cheng
28c85a81a1 Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 00:42:34 +00:00
Chandler Carruth
0682597817 Remove a file from CMakeLists.txt that Evan removed in r136027.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 00:30:33 +00:00
Evan Cheng
94b9550a32 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 00:24:13 +00:00
Chandler Carruth
b35552d440 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 00:09:08 +00:00
Evan Cheng
78c10eeaa5 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:24:55 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:09:14 +00:00
Bruno Cardoso Lopes
863bd9d5cf Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
This also fixes PR10452

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:32 +00:00
Bruno Cardoso Lopes
51e92e8e41 Add remaining 256-bit vector bitcasts. This also fixes PR10451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:28 +00:00
Bruno Cardoso Lopes
6a32adc4e5 - Handle special scalar_to_vector case: splats. Using a native 128-bit
shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:25 +00:00
Bruno Cardoso Lopes
233fa39245 Reintroduce r135730, this is indeed the right approach, there is no
native 256-bit vector instruction to do scalar_to_vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:16 +00:00
Benjamin Kramer
a3d782f40c Add a note about efficient codegen for binary log.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:30:00 +00:00
Jim Grosbach
580f4a9c1c ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:20:28 +00:00
Evan Cheng
617793d1d6 Refactoring fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:16:37 +00:00
Evan Cheng
f16f3476a2 Move CBackend and CppBackend MC initialization to TargetInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:44:12 +00:00
Eli Friedman
63f8dde482 Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask.
Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:36:45 +00:00
Evan Cheng
275944afb5 Fix more MC layering violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:32:49 +00:00
Evan Cheng
d1200aa4f8 More MC layering violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:29:26 +00:00
Rafael Espindola
5160d38166 Add LLVMAddTargetLibraryInfo to the C API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:20:54 +00:00
Evan Cheng
4b64e8a9e1 Separate MCInstPrinter registration from AsmPrinter registration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:20:24 +00:00
Jim Grosbach
e4616ace02 Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:04:58 +00:00
Evan Cheng
1b0fc9b418 Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:53:02 +00:00
Jim Grosbach
af6981f2f5 ARM asm operand renaming. Make things a bit more explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:49:51 +00:00