Commit Graph

116515 Commits

Author SHA1 Message Date
Jingyue Wu
728ad0157c Resurrect r235688
We should skip vector types which are not SCEVable.

test/CodeGen/NVPTX/sched2.ll passes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 04:22:39 +00:00
Jingyue Wu
f42450abb6 Revert r235688
Seems breaking builds


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 03:26:11 +00:00
Jingyue Wu
b55e9545f2 [NVPTX] Emits "generic()" depending on the original address space
Summary:
Fixes a bug in the NVPTX codegen. The code used to miss necessary "generic()"
on aggregates of addrspacecasts.

Test Plan: addrspacecast-gvar.ll

Reviewers: eliben, jholewinski

Reviewed By: jholewinski

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D9130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 02:57:30 +00:00
Jingyue Wu
d83b3b1a8d [NVPTX] enable NaryReassociate in NVPTX
Summary:
We run NaryReassociate right after SLSR because SLSR enables many
opportunities for NaryReassociate. For example, in nary-slsr.ll

  foo((a + b) + c);
  foo((a + b * 2) + c);
  foo((a + b * 3) + c);   // 2 muls and 6 adds

after SLSR:

  ab = a + b;
  foo(ab + c);
  ab2 = ab + b;
  foo(ab2 + c);
  ab3 = ab2 + b;
  foo(ab3 + c);           // 6 adds

after NaryReassociate:

  abc = (a + b) + c;
  foo(abc);
  ab2c = abc + b;
  foo(ab2c);
  ab3c = ab2c + b;
  foo(ab3c);              // 4 adds

Test Plan: nary-slsr.ll

Reviewers: jholewinski, eliben

Reviewed By: eliben

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D9066

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235688 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 02:54:06 +00:00
Matt Arsenault
9dd5b1fbd8 R600/SI: Fix verifier error when producing v_madmk_f32
Copy the kill flags when swapping the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235687 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 01:57:58 +00:00
Matthias Braun
d32beab637 Improve isTriviallyReMaterializable() documentation.
This should make it clear under which narrow circumstances implicit
physreg uses are okay when rematerializing and prevent people from
accidentally allowing too much when overriding
isReallyTriviallyReMaterializable() even with the weaker assert in the
RegisterCoalescer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235679 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 01:15:27 +00:00
Matthias Braun
bd112c28b5 R600/RegisterCoalescer: Enable more rematerialization/add missing testcase
This enables the rematerialization of some R600 MOV instructions in the
RegisterCoalescer and adds a testcase for r235668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235675 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 00:25:50 +00:00
Michael Zolotukhin
0683161523 Fix a couple of typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235674 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 00:10:27 +00:00
Matthias Braun
37f93d4cbf RegisterCoalescer: implicit phsreg uses are fine when rematerializing
The target hooks should have already checked them. This change is
necessary to enable the remateriailzation on R600.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235673 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 00:01:37 +00:00
Matt Arsenault
b638e142b4 Revert accidentally committed "MC: Allow targets to stop symbol name quoting"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235672 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:34:51 +00:00
Matt Arsenault
784f73714b R600/SI: Special case v_mov_b32 as really rematerializable
This should be fixed to properly understand all rematerializable
instructions while ignoring implicit reads of exec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:34:48 +00:00
Matt Arsenault
6ec2992aca MC: Allow targets to stop symbol name quoting
Currently symbol names are printed in quotes if it contains something
outside of the arbitrary set of characters that isAcceptableChar tests
for. On somem targets, it is never OK to print a symbol name in quotes
so allow targets to opt out of this behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235670 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:34:05 +00:00
Matthias Braun
589d8fd65d RegisterCoalescer: Avoid unnecessary register class widening for some rematerializations
I couldn't provide a testcase as none of the public targets has wide
register classes with alot of subregisters and at the same time an
instruction which "ReMaterializable" and "AsCheapAsAMove" (could
probably be added for R600).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235668 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:24:36 +00:00
Reid Kleckner
f87165820d Re-commit "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works"
This reverts commit r235617.

r235649 should have addressed the problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235667 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:22:33 +00:00
Richard Smith
04df402b09 Fix modules build post-r235612.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235666 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:22:26 +00:00
Hal Finkel
100eab89f5 [PowerPC] Support register name prefixes for vector registers
Match binutils by supporting the optional register name prefix for new vector
registers ("vs" for VSX registers and "q" for QPX registers).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:16:22 +00:00
Hal Finkel
ba03f542ac [PowerPC] Use sync inst alias when printing
So long as the choice between printing msync and sync is not ambiguous, we can
print 'sync 0' and just 'sync'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235663 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:05:08 +00:00
Tom Stellard
6d49b023a4 R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235662 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:59:24 +00:00
Michael Zolotukhin
9c0fb9467f Fix comment for NoCommonBits.
Maybe there is a better wording, but at least it should be technically
correct now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235660 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:55:48 +00:00
Hal Finkel
79f43b2736 [PowerPC] Add asm/disasm support for dcbt with hint
Add assembler/disassembler support for dcbt/dcbtst (and aliases) with the hint
field specified (non-zero). Unforunately, the syntax for this instruction is
special in that it differs for server vs. embedded cores:
   dcbt ra, rb, th [server]
   dcbt th, ra, rb [embedded]
where th can be omitted when it is 0. dcbtst is the same. Thus we need to play
games in the parser and the printer to flip the operands around on the embedded
cores. We'll use the server syntax as the default (binutils currently uses the
embedded form by default, but IBM is changing that).

We also stop marking dcbtst as having unmodeled side effects (this is not
necessary, it is just a hint like dcbt -- noticed by inspection, so no separate
test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:47:57 +00:00
Andrew Kaylor
3ad4bc1445 [WinEH] Ignore filter clauses while mapping landing pad blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235656 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 22:38:36 +00:00
Reid Kleckner
173a68d4a2 Remove trivial assert to fix NDEBUG Werror builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235652 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 21:36:32 +00:00
David Blaikie
93a23a3bd4 Recommit r235458: [opaque pointer type] Avoid using PointerType::getElementType for a few cases of CallInst
(reverted in r235533)

Original commit message:

"Calls to llvm::Value::mutateType are becoming extra-sensitive now that
instructions have extra type information that will not be derived from
operands or result type (alloca, gep, load, call/invoke, etc... ). The
special-handling for mutateType will get more complicated as this work
continues - it might be worth making mutateType virtual & pushing the
complexity down into the classes that need special handling. But with
only two significant uses of mutateType (vectorization and linking) this
seems OK for now.

Totally open to ideas/suggestions/improvements, of course.

With this, and a bunch of exceptions, we can roundtrip an indirect call
site through bitcode and IR. (a direct call site is actually trickier...
I haven't figured out how to deal with the IR deserializer's lazy
construction of Function/GlobalVariable decl's based on the type of the
entity which means looking through the "pointer to T" type referring to
the global)"

The remapping done in ValueMapper for LTO was insufficient as the types
weren't correctly mapped (though I was using the post-mapped operands,
some of those operands might not have been mapped yet so the type
wouldn't be post-mapped yet). Instead use the pre-mapped type and
explicitly map all the types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235651 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 21:36:23 +00:00
Reid Kleckner
d1807ff318 [WinEH] Replace more lpad value uses with undef
We were asserting on code like this:
  extern "C" unsigned long _exception_code();
  void might_crash(unsigned long);
  void foo() {
    __try {
      might_crash(0);
    } __except(1) {
      might_crash(_exception_code());
    }
  }

Gtest and many other libraries get the exception code from the __except
block. What's supposed to happen here is that EAX is live into the
__except block, and it contains the exception code. Eventually we'll
represent that as a use of the landingpad ehptr value, but for now we
can replace it with undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235649 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 21:22:30 +00:00
Quentin Colombet
c364314ec3 [MachineCopyPropagation] Handle undef flags conservatively so that we do not
remove copies that are useful after breaking some hardware dependencies.
In other words, handle this kind of situations conservatively by assuming reg2
is redefined by the undef flag.
reg1 = copy reg2
= inst reg2<undef>
reg2 = copy reg1
Copy propagation used to remove the last copy.
This is incorrect because the undef flag on reg2 in inst, allows next
passes to put whatever trashed value in reg2 that may help.
In practice we end up with this code:
reg1 = copy reg2
reg2 = 0
= inst reg2<undef>
reg2 = copy reg1

This fixes PR21743.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235647 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 21:17:39 +00:00
Krzysztof Parzyszek
9ed816ae52 Unbreak build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235646 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:57:39 +00:00
Krzysztof Parzyszek
b5ce56f874 [Hexagon] Minor cleanup in HexagonFrameLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235645 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:42:20 +00:00
Tom Stellard
2aab32cade R600/SI: Fix indirect addressing with a negative constant offset
When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.

In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235641 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:32:01 +00:00
Peter Collingbourne
391b2c39f7 Thumb2: When applying branch optimizations, visit branches in reverse order.
The order in which branches appear in ImmBranches is approximately their
order within the function body. By visiting later branches first, we reduce
the distance between earlier forward branches and their targets, making it
more likely that the cbn?z optimization, which can only apply to forward
branches, will succeed for those earlier branches.

Differential Revision: http://reviews.llvm.org/D9185

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235640 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:35 +00:00
Peter Collingbourne
1ad0f74155 ARM: When re-creating a branch via InsertBranch, preserve CPSR flags.
In particular, this preserves the kill flag, which allows the Thumb2 cbn?z
optimization to be applied in cases where a branch has been re-created after
the live variables analysis pass, e.g. by the machine block placement pass.

This appears to be low risk; a number of other targets seem to already be
doing something similar, e.g. AArch64, PowerPC.

Differential Revision: http://reviews.llvm.org/D9184

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235639 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:32 +00:00
Peter Collingbourne
d9a479e5a0 Thumb2: When optimizing for size, do not if-convert branches involving comparisons with zero.
This allows the constant island pass to lower these branches to cbn?z
instructions, resulting in a shorter instruction sequence.

Differential Revision: http://reviews.llvm.org/D9183

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:30 +00:00
Peter Collingbourne
f86c29ea2c ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.
This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:26 +00:00
Peter Collingbourne
b28abbf98b ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.
This appears to have been introduced back in r76698 as part of an unrelated
change. I can find no official ARM documentation stating that Thumb-2 functions
require 4-byte alignment; in fact, ARM documentation appears to contradict
this (see, e.g., ARM Architecture Reference Manual Thumb-2 Supplement,
section 2.6.1: "Thumb-2 enforces 16-bit alignment on all instructions.").

Also remove code that sets alignment for ARM functions, which is redundant
with code in the MachineFunction constructor, and remove the hidden
-arm-align-constant-islands flag, which has been enabled by default since
r146739 (Dec 2011) and has probably received sufficient testing by now.

Differential Revision: http://reviews.llvm.org/D9138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:22 +00:00
Krzysztof Parzyszek
ab740d1e40 [Hexagon] Fix compiler warnings in release build
Patch by Aditya Nandakumar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235635 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:26:21 +00:00
Adam Nemet
50b9e7f7d4 [getUnderlyingOjbects] Analyze loop PHIs further to remove false positives
Specifically, if a pointer accesses different underlying objects in each
iteration, don't look through the phi node defining the pointer.

The motivating case is the underlyling-objects-2.ll testcase.  Consider
the loop nest:

  int **A;
  for (i)
    for (j)
       A[i][j] = A[i-1][j] * B[j]

This loop is transformed by Load-PRE to stash away A[i] for the next
iteration of the outer loop:

  Curr = A[0];          // Prev_0
  for (i: 1..N) {
    Prev = Curr;        // Prev = PHI (Prev_0, Curr)
    Curr = A[i];
    for (j: 0..N)
       Curr[j] = Prev[j] * B[j]
  }

Since A[i] and A[i-1] are likely to be independent pointers,
getUnderlyingObjects should not assume that Curr and Prev share the same
underlying object in the inner loop.

If it did we would try to dependence-analyze Curr and Prev and the
analysis of the corresponding SCEVs would fail with non-constant
distance.

To fix this, the getUnderlyingObjects API is extended with an optional
LoopInfo parameter.  This is effectively what controls whether we want
the above behavior or the original.  Currently, I only changed to use
this approach for LoopAccessAnalysis.

The other testcase is to guard the opposite case where we do want to
look through the loop PHI.  If we step through an array by incrementing
a pointer, the underlying object is the incoming value of the phi as the
loop is entered.

Fixes rdar://problem/19566729

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:09:20 +00:00
Jingyue Wu
12f341611a [NVPTX] run SeparateConstOffsetFromGEP before SLSR
Summary:
We pick this order because SeparateConstOffsetFromGEP may create more
opportunities for SLSR.

Test Plan:
reassociate-geps-and-slsr.ll
no performance regression on internal benchmarks

Reviewers: meheff

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D9230

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235632 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:00:04 +00:00
Tom Stellard
e32631cecd R600/SI: Add missing -mcpu=SI to assembler test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235630 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:55 +00:00
Tom Stellard
59edae9b85 R600/SI: Add assembler support for all CI and VI VOP1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235629 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:54 +00:00
Tom Stellard
f0924551e6 R600/SI: v_mov_fed_b32 does not exist on VI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235628 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:52 +00:00
Tom Stellard
bf02414898 R600/SI: Use a better error message for unsupported instructions in the assembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235627 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:51 +00:00
Tom Stellard
95081f5241 R600/SI: Improve AsmParser support for forced e64 encoding
We can now force e64 encoding even when the operands would be legal
for e32 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235626 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 19:33:48 +00:00
Andrew Kaylor
71ed98da5c [WinEH] Handle stubs for outlined functions that have only unreached terminators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235618 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 18:37:39 +00:00
Reid Kleckner
70e56ae6b3 Revert "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works"
We still have some "uses remain after removal" issues in -O0 builds.

This reverts commit r235557.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235617 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 18:34:01 +00:00
Hal Finkel
184f8f7c10 [PowerPC] Enable printing instructions using aliases
TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 18:30:38 +00:00
Zachary Turner
45e7e93c6f Move DIContext.h to common DebugInfo location.
This will enable us to create a PDBContext so as to expose some
amount of debug info functionality through a common interace.

Differential Revision: http://reviews.llvm.org/D9205
Reviewed by: Alexey Samsonov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235612 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 17:37:47 +00:00
Philip Reames
1aa9710c60 Move Value.isDereferenceablePointer to ValueTracking [NFC]
Move isDereferenceablePointer function to Analysis. This function recursively tracks dereferencability over a chain of values like other functions in ValueTracking.

This refactoring is motivated by further changes to support dereferenceable_or_null attribute (http://reviews.llvm.org/D8650). isDereferenceablePointer will be extended to perform context-sensitive analysis and IR is not a good place to have such functionality.

Patch by: Artur Pilipenko <apilipenko@azulsystems.com>
Differential Revision: reviews.llvm.org/D9075




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 17:36:48 +00:00
Pirama Arumuga Nainar
dab5145cb3 [AArch64] Add nvcast patterns for v4f16 and v8f16
Summary:
Constant stores of f16 vectors can create NvCast nodes from various
operand types to v4f16 or v8f16 depending on patterns in the stored
constants.  This patch adds nvcast rules with v4f16 and v8f16 values.

AArchISelLowering::LowerBUILD_VECTOR has the details on which constant
patterns generate the nvcast nodes.

Reviewers: jmolloy, srhines, ab

Subscribers: rengolin, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D9201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235610 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 17:32:25 +00:00
Pirama Arumuga Nainar
b7db5f28c5 [AArch64] Handle vec4, vec8, vec16 *itofp for half
Summary:
Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32,
v8i8, v8i16 inputs to allow promotion of v4f16 results.

Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32,
and i64 vectors.  Only missing tests are for v16i8 and v16i16 as the
shift operations are too complicated to write a proper check sequence.

The conversions from v4i64 to v4f16 do not depend on this patch - v4i64
is split and the conversion gets handled while lowering v2i64.  I am
adding a test here for completeness.

Reviewers: aemerson, rengolin, ab, jmolloy, srhines

Subscribers: rengolin, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D9166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 17:16:27 +00:00
Hans Wennborg
defaf830f9 Re-commit r235560: Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)
Third time's the charm. The previous commit was reverted as a
reverse for-loop in SelectionDAGBuilder::lowerWorkItem did 'I--'
on an iterator at the beginning of a vector, causing asserts
when using debugging iterators. This commit fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 16:45:24 +00:00
Sanjay Patel
08aea0a553 use update_llc_test_checks.py to tighten checking; remove unnecessary CPU param
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235604 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 16:07:50 +00:00