Commit Graph

82197 Commits

Author SHA1 Message Date
Manman Ren
1701105022 test/CodeGen/X86/select.ll: remove spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 18:54:27 +00:00
Chad Rosier
238ae31aa3 Tidy up. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 17:47:15 +00:00
Derek Schuff
ddc693bd22 Fix fastcc structure return with fast-isel on x86-32
On x86-32, structure return via sret lets the callee pop the hidden
pointer argument off the stack, which the caller then re-pushes.
However if the calling convention is fastcc, then a register is used
instead, and the caller should not adjust the stack. This is
implemented with a check of IsTailCallConvention
X86TargetLowering::LowerCall but is now checked properly in
X86FastISel::DoSelectCall.

(this time, actually commit what was reviewed!)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 16:57:15 +00:00
Bob Wilson
ff73d8fef9 Don't introduce illegal types when creating vmull operations. <rdar://11324364>
ARM BUILD_VECTORs created after type legalization cannot use i8 or i16
operands, since those types are not legal.  Instead use i32 operands, which
will be implicitly truncated by the BUILD_VECTOR to match the element type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 16:53:34 +00:00
Eli Bendersky
37bc5a2000 It doesn't make sense to move symbol relocations to section relocations when
relocations are resolved.  It's much more reasonable to do this decision when
relocations are just being added - we have all the information at that point.

Also a bit of renaming and extra comments to clarify extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 12:15:58 +00:00
Duncan Sands
5ff30e70f8 Just mark the sign bit as known zero, rather than any other irrelevant bits
known zero in the LHS.  Fixes PR12541.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 11:56:58 +00:00
Bill Wendling
bfbab99b58 Second attempt at PR12573:
Allow the "SplitCriticalEdge" function to split the edge to a landing pad. If
the pass is *sure* that it thinks it knows what it's doing, then it may go ahead
and specify that the landing pad can have its critical edge split. The loop
unswitch pass is one of these passes. It will split the critical edges of all
edges coming from a loop to a landing pad not within the loop. Doing so will
retain important loop analysis information, such as loop simplify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 10:44:54 +00:00
Bill Wendling
38da2a8cc1 Use an ArrayRef instead of explicit vector type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 10:25:51 +00:00
Eli Bendersky
6d15e87177 Code cleanup in RuntimeDyld:
- Add comments
- Change field names to be more reasonable
- Fix indentation and naming to conform to coding conventions
- Remove unnecessary includes / replace them by forward declatations



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 10:06:27 +00:00
Bill Wendling
6aa33274ed Remove hack from r154987. The problem persists even with it, so it's not even a good hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 09:23:48 +00:00
Craig Topper
7d1e3dcf71 No need to normalize index before calling Extract128BitVector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 05:17:10 +00:00
Pete Cooper
6942f706aa Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT emitter. Needs some major refactoring as these two code emitters are almost identical
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155810 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 03:56:44 +00:00
Rafael Espindola
9719cf329b Make sure HoistInsertPosition finds a position that is dominated by all
inputs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 03:53:06 +00:00
Jakub Staszak
6610b1db55 Remove unneeded casts. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 20:52:53 +00:00
Craig Topper
7988981990 Remove superfluous 'inline'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 20:27:47 +00:00
Craig Topper
d77d2feb7a Simplify code a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 20:22:05 +00:00
Kalle Raiskila
a04fe83378 Update the documentation of CellSPU, in case it gets removed in 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 20:00:55 +00:00
Benjamin Kramer
2b8d0501b1 RegisterPressure: ArrayRefize some functions for better readability. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 18:52:56 +00:00
Eli Bendersky
5fe019835c Fix some formatting, grammar and style issues and add a couple of missing comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 12:40:47 +00:00
Eli Bendersky
30183bf042 Remove redundant line (the memory manager is set above to the same object
if !ForceInterpreteri). It has no effect (apart from a memory leak...)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 11:14:59 +00:00
Benjamin Kramer
3703baacf5 SmallVector: Don't rely on having an assignment operator around in push_back for POD-like types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155791 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 10:53:29 +00:00
Eli Bendersky
bbd8e5d79a Fix comments from copy-paste to a more relevant meaning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 10:26:26 +00:00
Craig Topper
db0bbdea47 Add constants for first and last integer vector types to be consistent with floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 07:25:46 +00:00
Craig Topper
c7f7a9ba79 Remove tab characters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 07:07:36 +00:00
Craig Topper
9efb030911 Mark the default cases of MVT::getVectorElementType and MVT:getVectorNumElements as unreachable to reduce code size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 07:06:58 +00:00
Jakob Stoklund Olesen
ff11c01853 Don't update spill weights when joining intervals.
We don't compute spill weights until after coalescing anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 19:19:11 +00:00
Jakob Stoklund Olesen
f4aee4c50e Spring cleaning - Delete dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 19:19:07 +00:00
Benjamin Kramer
18883037a9 If the __is_trivially_copyable type trait is available use it as the baseline for isPodLike.
This way we can enable the POD-like class optimization for a lot more classes,
saving ~120k of code in clang/i386/Release+Asserts when selfhosting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 16:22:31 +00:00
Benjamin Kramer
1dd346ad05 Use the most basic superclass of SmallVector in ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 16:22:26 +00:00
Jakob Stoklund Olesen
9b10dae0bf Fix a problem with blocks that need to be split twice.
The code could search past the end of the basic block when there was
already a constant pool entry after the block.

Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 06:21:38 +00:00
Andrew Trick
2674a4acdb Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.
This time, also fix the caller of AddGlue to properly handle
incomplete chains. AddGlue had failure modes, but shamefully hid them
from its caller. It's luck ran out.

Fixes rdar://11314175: BuildSchedUnits assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-28 01:03:23 +00:00
Jim Grosbach
a9cc08f24f ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:51:36 +00:00
Jim Grosbach
bb32f1d545 ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:51:33 +00:00
Derek Schuff
f3db6b855e Revert r155745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:37:41 +00:00
Derek Schuff
9dc28b0722 Fix fastcc structure return with fast-isel on x86-32
On x86-32, structure return via sret lets the callee pop the hidden
pointer argument off the stack, which the caller then re-pushes.
However if the calling convention is fastcc, then a register is used
instead, and the caller should not adjust the stack. This is
implemented with a check of IsTailCallConvention
X86TargetLowering::LowerCall but is now checked properly in
X86FastISel::DoSelectCall.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:27:17 +00:00
Jakob Stoklund Olesen
456ff46e66 Track worst case alignment padding more accurately.
Previously, ARMConstantIslandPass would conservatively compute the
address of an aligned basic block as:

  RoundUpToAlignment(Offset + UnknownPadding)

This worked fine for the layout algorithm itself, but it could fool the
verify() function because it accounts for alignment padding twice: Once
when adding the worst case UnknownPadding, and again by rounding up the
fictional block offset. This meant that when optimizeThumb2Instructions
would shrink an instruction, the conservative distance estimate could
grow. That shouldn't be possible since the woorst case alignment padding
wss already included.

This patch drops the use of RoundUpToAlignment, and depends only on
worst case padding to compute conservative block offsets. This has the
weird effect that the computed offset for an aligned block may not be
aligned.

The important difference is that shrinking an instruction can never
cause the estimated distance between two instructions to grow. The
estimated distance is always larger than the real distance that only the
assembler knows.

<rdar://problem/11339352>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:58:38 +00:00
Andrew Trick
0e47cfd5b6 Temporarily revert r155668: Fix the SD scheduler to avoid gluing.
This definitely caused regression with ARM -mno-thumb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:55:59 +00:00
Craig Topper
66ddd153f6 Use 'unsigned' instead of 'int' in several places when retrieving number of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:54:43 +00:00
Chad Rosier
a73b6fc511 Add x86-specific DAG combine to simplify:
x == -y --> x+y == 0
 x != -y --> x+y != 0

On x86, the generated code goes from
   negl    %esi
   cmpl    %esi, %edi
   je    .LBB0_2
to
   addl    %esi, %edi
   je    .L4

This case is correctly handled for ARM with "cmn".

Patch by Manman Ren.
rdar://11245199
PR12545


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155739 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:33:25 +00:00
Michael J. Spencer
57d61de858 [Support/YAMLParser] Fix ASan found bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 21:12:20 +00:00
Craig Topper
b4a8aef96d Tidy up spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 21:05:09 +00:00
Evan Cheng
da71cca458 Make test less fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 20:48:18 +00:00
Hal Finkel
e32e5440d6 Don't vectorize target-specific types (ppc_fp128, x86_fp80, etc.).
Target specific types should not be vectorized. As a practical matter,
these types are already register matched (at least in the x86 case),
and codegen does not always work correctly (at least in the ppc case,
and this is not worth fixing because ppc_fp128 is currently broken and
will probably go away soon).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 19:34:00 +00:00
David Blaikie
f6d55df9ec Change recurse depth limit to uint32 to fix warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 19:30:32 +00:00
David Blaikie
ca63acdc5d Switch to c-style comments in a C file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 19:30:29 +00:00
Dan Gohman
447989cb68 Miscellaneous accumulated cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 18:56:31 +00:00
Lang Hames
7787800481 Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
<rdar://problem/11325085>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 18:51:24 +00:00
Mon P Wang
5dde20bfac Add an early bailout to IsValueFullyAvailableInBlock from deeply nested blocks.
The limit is set to an arbitrary 1000 recursion depth to avoid stack overflow
issues. <rdar://problem/11286839>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 18:09:28 +00:00
Dan Gohman
03e091f0b5 Reapply r155682, making constant folding more consistent, with a fix to work
properly with how the code handles all-undef PHI nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 17:50:22 +00:00
Richard Barton
04a09a461b Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 17:34:01 +00:00