Commit Graph

22470 Commits

Author SHA1 Message Date
Craig Topper
7a9a28b2c9 Make replace many calls to getSizeInBits() with is128BitVector/is256BitVector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12 02:23:29 +00:00
Craig Topper
0d1f176b3f Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation actions. Compiles to smaller code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12 00:34:56 +00:00
Michael Liao
9eac20ac88 fix PR13577, an issue introduced by r161687
- FCMOV only supports a subset of X86 conditions. Skip boolean
  simplification if X86 condition is not valid for FCMOV.
- add a minimal test case for PR13577.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 23:47:06 +00:00
Craig Topper
880ef45a14 Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop since all 256-bit types are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 22:34:26 +00:00
Craig Topper
f4cfc4423c Tidy up indentation. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 17:53:00 +00:00
Craig Topper
dca72541d5 Fix a cast that was casting away 'const' unnecessarily
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 17:46:16 +00:00
Craig Topper
2865422a4d Add a couple default: llvm_unreachable() to some switch statements. Fix a bad message in an existing llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 17:44:14 +00:00
Manman Ren
743a2cff04 X86: when we are auto-detecting the subtarget features, make sure we turn on
FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge.

FeatureFastUAMem is already on if we pass in nehalem or westmere as a command
argument.

rdar: 7252306


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 23:43:32 +00:00
Manman Ren
d9b4512593 ARM: enable struct byval for AAPCS.
This change is to be enabled in clang.

rdar://9877866
PR://13350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161693 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 20:39:38 +00:00
Michael Liao
2a33cec66a add X86-specific DAG optimization to simplify boolean test
- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value
  generated from X86ISD::SETCC, try to simplify the boolean value
  generation and checking by reusing the original EFLAGS with proper
  condition code
- add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places
  consuming EFLAGS

part of patches fixing PR12312



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 19:58:13 +00:00
Michael Liao
f6c24eef62 remove tailing whitespaces and test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 14:39:24 +00:00
Joerg Sonnenberger
78cab947cf Add some missing includes for the build against stdcxx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 10:53:56 +00:00
Eric Christopher
df1c637ac4 Remove getARMRegisterNumbering and replace with calls into
the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.

One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:10:21 +00:00
Jakob Stoklund Olesen
69a0aa87f8 Don't modify MO while use_iterator is still pointing to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:08:24 +00:00
Chad Rosier
3246176838 [ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).
This new API will be used by clang to parse ms-style inline asms.

One goal of this project is to use this style of inline asm for targets other
then x86.  Therefore, this API needs to be implemented for non-x86 targets at
some point in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 22:04:55 +00:00
Jack Carter
8d7e5efcaa Another 32 to 64 bit sign extension bug.
The fields in the td definition were switched.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 19:43:18 +00:00
Arnold Schwaighofer
bcc4c1d2d1 Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.

Bug 12213

Patch by Yin Ma!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 15:25:52 +00:00
Eric Christopher
529f314050 This field isn't used anymore, use it with HWEncoding instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09 01:39:32 +00:00
Jakob Stoklund Olesen
0c5f5f4916 Don't use getNextOperandForReg().
This way of using getNextOperandForReg() was unlikely to work as
intended. We don't give any guarantees about the order of operands in
the use-def chains, so looking only at operands following a given
operand in the chain doesn't make sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 23:44:04 +00:00
Andrew Trick
d43b5c97cf Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 02:44:16 +00:00
Andrew Trick
d598bd3aee whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161469 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 02:44:08 +00:00
Manman Ren
39ad568c62 X86: enable CSE between CMP and SUB
We perform the following:
1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering.
2> Modify MachineCSE to correctly handle implicit defs.
3> Convert SUB back to CMP if possible at peephole.

Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled
by peephole now.

rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 00:51:41 +00:00
Jakob Stoklund Olesen
130e603115 Don't scan physreg use-def chains looking for a PIC base.
We can't rematerialize a PIC base after register allocation anyway, and
scanning physreg use-def chains is very expensive in a function with
many calls.

<rdar://problem/12047515>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 00:40:47 +00:00
Evan Cheng
b64dd5f2b5 X86 cmp lowering is looking past truncate on the condition node. It should only
do so when the high bits are known zero. This caused a subtle miscompilation.

rdar://12027825 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 22:21:00 +00:00
Hal Finkel
8da94ad6e0 Add a comment about mftb vs. mfspr on PPC.
Thanks to Alex Rosenberg for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 17:04:20 +00:00
Bill Wendling
cbfce45577 Revert r161371. Removing the 'const' before Type is a "good thing".
--- Reverse-merging r161371 into '.':
U    include/llvm/Target/TargetData.h
U    lib/Target/TargetData.cpp



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161394 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 05:51:59 +00:00
Jack Carter
5b0e9ce2e5 The define for 64 bit sign extension neglected to
initialize fields of the class that it used.

The result was nonsense code.

Before:
0000000000000000 <foo>:
   0:    00441100     0x441100
   4:    03e00008     jr    ra
   8:    00000000     nop

After:
0000000000000000 <foo>:
   0:    00041000     sll    v0,a0,0x0
   4:    03e00008     jr    ra
   8:    00000000     nop 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 00:35:22 +00:00
Bill Wendling
121418e551 Constify the Type parameter to some methods (which are const anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161371 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 00:26:35 +00:00
Andrew Trick
c42a701786 Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.
This allows codegen passes to query properties like
InstrItins->SchedModel->IssueWidth. It also ensure's that
computeOperandLatency returns the X86 defaults for loads and "high
latency ops". This should have no significant impact on existing
schedulers because X86 defaults happen to be the same as global
defaults.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 00:25:30 +00:00
Jack Carter
e2245bab3c Mips relocation R_MIPS_64 relocates a 64 bit double word.
I hit this in a very large program (spirit.cpp), but 
have not figured out how to make a small make check
test for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07 00:01:14 +00:00
Jack Carter
61de70d98e The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
were using a class defined for 32 bit instructions and 
thus the instruction was for addiu instead of daddiu.

This was corrected by adding the instruction opcode as a 
field in the  base class to be filled in by the defs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 23:29:06 +00:00
Jack Carter
fc54d9e47a Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.
These 2 relocations gain access to the 
highest and the second highest 16 bits
of a 64 bit object.

R_MIPS_HIGHER %higher(A+S)
The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. 

R_MIPS_HIGHEST %highest(A+S)
The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161348 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 21:26:03 +00:00
Hal Finkel
f45717e985 MFTB on PPC64 should really be encoded using MFSPR.
The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.

Thanks to Adhemerval Zanella for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 21:21:44 +00:00
Eric Christopher
b0f6759ab9 Add support for the OpenBSD for Bitrig.
Patch by David Hill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 20:52:18 +00:00
Roman Divacky
e76c903bd2 Remove empty overrides of processFunctionBeforeFrameFinalized().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 18:14:18 +00:00
Craig Topper
4feb647283 Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 06:22:36 +00:00
Craig Topper
cc915951eb Remove custom inserter for MWAIT. It doesn't do anything that couldn't be represented in a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05 00:36:57 +00:00
Craig Topper
638aa687d4 Use a COPY node instead of an explicit MOVA opcode in the custom insterter for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05 00:17:48 +00:00
Hal Finkel
8cc3474f72 Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 14:10:46 +00:00
Anton Korobeynikov
ad62e92279 Skip impdef regs during eabi save/restore list emission to workaround PR11902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 13:25:58 +00:00
Anton Korobeynikov
161474d198 Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack stuff
(this corresponds by spilling/reloading regs in DTriple / DQuad reg classes).
No testcase, found by inspection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 13:22:14 +00:00
Anton Korobeynikov
b58d7d0312 Add stack spill / reload instructions for DTriple and DQuad register classes, which
were missed for no reason. This fixes PR13377


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 13:16:12 +00:00
Akira Hatanaka
24e79e55da 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 22:57:02 +00:00
Gabor Greif
4ecaedc771 allow 'make CPPFLAGS=<something>' work again
this makes this hack a bit more bearable
for poor souls who need to pass custom
preprocessor flags to the build process

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 13:31:24 +00:00
Bob Wilson
d49edb7ab0 Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions.  For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization.  Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel.  <rdar://problem/12008746>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 04:06:28 +00:00
Bob Wilson
d1e672e023 Add new getLibFunc method to TargetLibraryInfo.
This just provides a way to look up a LibFunc::Func enum value for a
function name.  Alphabetize the enums and function names so we can use a
binary search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161231 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 04:06:22 +00:00
Jush Lu
2946549a28 [arm-fast-isel] Add support for shl, lshr, and ashr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 02:37:48 +00:00
Eric Christopher
e94ac8871a Add support for the ARM GHC calling convention, this patch was in 3.0,
but somehow managed to be dropped later.

Patch by Karel Gardas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 00:05:53 +00:00
Jim Grosbach
55499db9a0 ARM: Tidy up. Remove unused template parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 22:08:27 +00:00
Jim Grosbach
9249ef3b99 ARM: More InstAlias refactors to use #NAME#.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161220 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 21:59:52 +00:00