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57 Commits

Author SHA1 Message Date
Nate Begeman
e179584f9b Change how FP immediates are handled. 
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-14 08:57:00 +00:00
Chris Lattner
834f1ce031 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 23:38:27 +00:00
Chris Lattner
2e48a70b35 rename isStore -> mayStore to more accurately reflect what it captures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 08:36:04 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Evan Cheng
6e141fd048 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-12 23:12:09 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Chris Lattner
0d75f57f75 implement anyextend from i1 -> i64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36802 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-05 22:17:00 +00:00
Duraid Madina
f525eb9056 fix storing bools to mem and unordered FP ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31920 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-26 04:34:26 +00:00
Evan Cheng
ca3202893c Remove a duplicate pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29414 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-31 18:43:10 +00:00
Duraid Madina
1ffd41ab99 doo de doo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26614 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 06:18:46 +00:00
Duraid Madina
631a140054 now short immediates will get matched (previously constants were all 
triggering movl 64bit imm fat instructions)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26119 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-11 07:32:15 +00:00
Chris Lattner
cedc6f4b30 PHI and INLINEASM are now built-in instructions provided by Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 01:46:15 +00:00
Duraid Madina
d92f116a1c some hoovering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25643 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 09:08:31 +00:00
Duraid Madina
badf0d9614 add bundling! well not really, for now it's just stop-insertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25593 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 02:23:38 +00:00
Duraid Madina
bea99471c7 remove RET hack, add proper support for rets (watching out for ret voids) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25486 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-20 20:24:31 +00:00
Duraid Madina
a7fb5bef55 fix storing bools! eek! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25476 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-20 03:40:25 +00:00
Duraid Madina
12f1bea6e2 fix boolean XOR (which fixes up comparisons..) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25462 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-19 15:18:56 +00:00
Duraid Madina
362071d7d4 use proper (82-bit) spills/fills when spilling FP regs, so that 
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25385 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-17 02:04:52 +00:00
Duraid Madina
0c81dc887c fix division! again!! pattern isel, prepare to die. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25353 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 06:33:38 +00:00
Duraid Madina
eac2a1bdbf this just might work 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25195 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 01:38:07 +00:00
Duraid Madina
07ac89f30a add support for selecting bools 
FIXME: this is commented out because it makes tblgen go a bit fruity


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25193 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-11 01:21:12 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-26 09:11:45 +00:00
Duraid Madina
806b89382a we don't feed our call instructions extra operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25009 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-25 14:07:01 +00:00
Duraid Madina
3d821e26a1 oops, back this out 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24950 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-22 07:13:51 +00:00
Duraid Madina
0b3c4d8221 we need to emit the getf.d instruction in lowering, so add it 
to IA64ISD


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24946 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-22 06:38:38 +00:00
Duraid Madina
a0a11d289d update tablegen files - nothing to see here 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24939 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-22 03:56:03 +00:00
Chris Lattner
b5d01436e3 Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24595 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:34:29 +00:00
Duraid Madina
889649e78e add FP select. next up - divide! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24346 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-14 01:17:30 +00:00
Duraid Madina
49fcc4006c fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24175 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-04 00:57:56 +00:00
Duraid Madina
0e5e0d14a8 add pattern to load constant 0 into a predicate reg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24164 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-03 10:09:32 +00:00
Chris Lattner
61bc60fc4f Fix a bug that prevented this pattern from matching 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24161 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-03 05:45:34 +00:00
Chris Lattner
cb2583e17d This works now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24150 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-02 06:49:37 +00:00
Duraid Madina
5966955445 add support for SELECT to TargetSelectionDAG.td, add support for 
selecting ints to IA64, and a few other ia64 bits and pieces


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24147 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-02 02:37:18 +00:00
Duraid Madina
aba8457125 so tablegen was thinking I might want to convert FPs to predicates. 
clever little tablegen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24133 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-01 03:32:15 +00:00
Duraid Madina
e2fd9e2d9d add support for int->FP and FP->int ops, and add ia64 patterns for these 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24132 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-01 03:07:25 +00:00
Duraid Madina
d1eda6d155 add zeroextend predicate->integer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24131 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-01 01:29:55 +00:00
Duraid Madina
363aff2f3c add FP compares and implicit register defs to the dag isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24118 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-31 01:42:11 +00:00
Duraid Madina
5c2c64e567 fix some broken comparisons, this affected the Pattern isel too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24109 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-30 10:14:19 +00:00
Duraid Madina
25d0a88eb8 add some FP stuff, some mix.* stuff, and constant pool support to the 
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24094 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-29 16:08:30 +00:00
Duraid Madina
274ecfb782 add shladd 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24080 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-29 04:13:40 +00:00
Duraid Madina
f2db9b88da DAG->DAG instruction selection for ia64! "hello world" works, not much else. 
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24058 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-28 17:46:35 +00:00
Chris Lattner
2e3f5db9ff Give all operands names 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23357 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-14 21:11:13 +00:00
Chris Lattner
efc58be8ca Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. 
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22892 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:47:42 +00:00
Duraid Madina
63bbed536c add the popcount instruction and support this in the isel 
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21860 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-05-11 05:16:09 +00:00
Duraid Madina
1ce0c015ad print negative 64 bit immediates as negative numbers, makes things a little 
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21300 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 10:08:01 +00:00
Duraid Madina
ed09502a0b * add the shladd instruction 
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21282 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-13 06:12:04 +00:00
Chris Lattner
ea6f770fb0 Make sure to realize that calls use their argument regs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21248 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 15:12:19 +00:00
Duraid Madina
5ef2ec9929 assorted fixes: 
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 05:55:56 +00:00
Duraid Madina
6dcceb5ecb fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn) 
fix hack in division (clean up frcpa instruction)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21153 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-08 10:01:48 +00:00