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8638692362
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3950 Commits

Author SHA1 Message Date
Jim Grosbach
8638692362 Simplify T2 operand assignment notation a bit. No need to specify a bit range 
for the source field when it's the whole thing that's being referenced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 22:10:43 +00:00
Jim Grosbach
0c2c217244 Tweak ARM fixup value adjustments for Thumb to better handle the half-word 
ordering of thumb mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 20:32:07 +00:00
Andrew Trick
6b1207267f Generalize PostRAHazardRecognizer so it can be used in any pass for 
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 20:04:29 +00:00
Owen Anderson
cc78f5c09c Improve comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 19:31:11 +00:00
Jim Grosbach
022ab3779c Add initializer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 15:36:45 +00:00
Evan Cheng
275bf63115 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 06:29:02 +00:00
Bill Wendling
b8958b031e Add support for loading from a constant pool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 01:57:09 +00:00
Jim Grosbach
5be6d2af38 Let target asm backends see assembler flags as they go by. Use that to handle 
thumb vs. arm mode differences in WriteNopData().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 01:16:55 +00:00
Owen Anderson
255eafbd49 Simplify the byte reordering logic slightly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 00:21:33 +00:00
Owen Anderson
d8e351b96f VLDR fixups need special handling under Thumb. While the encoding is the same, 
the order of the bytes in the data stream is flipped around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay
2bf315f087 Fix a warning about a variable which is only used in an assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:26:21 +00:00
Bill Wendling
d832fa053b Cleanup in the Darwin end. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:11:00 +00:00
Evan Cheng
06d65f5156 Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal 
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}

vpush and vpop do not allow gaps in the register list.
rdar://8728956


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:08:38 +00:00
Bill Wendling
52e635ea35 A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No 
functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:05:20 +00:00
Jim Grosbach
d967cd096a Binary encoding for ARM tLDRspi and tSTRspi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 21:50:47 +00:00
Owen Anderson
bdf714450b Fix Thumb2 encoding of the S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:50:15 +00:00
Jim Grosbach
97a884d602 Refactor the ARM CMPz* patterns to just use the normal CMP instructions when 
possible. They were duplicates for everything exception the source pattern
before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:41:06 +00:00
Evan Cheng
52f21e35e8 Code clean up; no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 20:11:46 +00:00
Evan Cheng
9801b5c822 Code clean up; no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:59:34 +00:00
Jim Grosbach
5169220624 Encode the literal field for tCMPzi instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121153 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 17:48:24 +00:00
Benjamin Kramer
6aa4943599 Add parens to pacify gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121142 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 15:50:35 +00:00
Jay Foad
40f8f6264d PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and 
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 08:25:19 +00:00
Owen Anderson
eb6779c5b9 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 00:45:21 +00:00
Jim Grosbach
662a816e89 Add fixup for Thumb1 BL/BLX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 23:57:07 +00:00
Rafael Espindola
179821ac1f Remove the instruction fragment to data fragment lowering since it was causing 
freed data to be read. I will open a bug to track it being reenabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 19:08:48 +00:00
Owen Anderson
c76c59840b Revert r121021, which broke the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:57:40 +00:00
Jim Grosbach
ba3368ceae Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121024 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:47:44 +00:00
Owen Anderson
4c386fc754 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:35:51 +00:00
Jim Grosbach
04f74942f2 Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if 
the instruction is predicated, reg0 otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:30:57 +00:00
Jim Grosbach
d67641b6f8 The ARM AsmMatcher needs to know that the CCOut operand is a register value, 
not an immediate. It stores either ARM::CPSR or reg0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 18:21:12 +00:00
Evan Cheng
04e2b639c1 Eliminate unneeded #include's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120971 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
714e07f75d ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120966 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:08:57 +00:00
Evan Cheng
167be80ee7 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:03:45 +00:00
Evan Cheng
f79ed109ec Remove an unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 23:03:35 +00:00
Evan Cheng
48575f6ea7 Making use of VFP / NEON floating point multiply-accumulate / subtraction is 
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-05 22:04:16 +00:00
Bob Wilson
c24130bade The Thumb tADDrSPi instruction is not valid when the destination is SP. 
Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 04:40:19 +00:00
Jim Grosbach
ceab50198e Encode condition code for Thumb1 conditional branch instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120865 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 00:20:40 +00:00
Jim Grosbach
ed09087dd3 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:54:18 +00:00
Bill Wendling
fb62d550de Use correct variable names to match the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:44:24 +00:00
Jim Grosbach
1b555d9f96 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120852 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 23:21:25 +00:00
Jim Grosbach
4fa102b84e Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:33:42 +00:00
Jim Grosbach
d91f4e40e6 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:31:40 +00:00
Jim Grosbach
41ad0c4c73 When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 20:33:01 +00:00
Benjamin Kramer
b3a04d46e8 Remove unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:55:37 +00:00
Jim Grosbach
6e57298127 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:47:11 +00:00
Jason W Kim
2ccf148fba fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120832 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:40:23 +00:00
Jim Grosbach
0b951ceb02 No need to declare EncoderMethod property anymore; just assign to it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 19:31:00 +00:00
Jim Grosbach
d253545c17 Add FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 18:37:17 +00:00
Jim Grosbach
2c971ab9d9 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 18:31:03 +00:00
Bill Wendling
278b6e81c8 Don't overwrite the opcode passed into the T1Special pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 02:02:58 +00:00