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8834559626
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21709 Commits

Author SHA1 Message Date
David Blaikie
8834559626 Remove unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 18:10:13 +00:00
Jim Grosbach
199366a6a6 ARM assembly two-operand forms for VRSHL. 
rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 18:03:16 +00:00
Akira Hatanaka
3ef7edc77a Do not add offset in applyFixup. This has already been accounted for in Value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154838 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 18:00:19 +00:00
Jim Grosbach
705e2572b4 ARM two-operand aliases for VRHADD instructions. 
rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 17:14:11 +00:00
Sirish Pande
87eb92d913 Hexagon V5 (Floating Point) Support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154829 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 17:05:06 +00:00
Craig Topper
ffa6c40ecf Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154801 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 07:13:00 +00:00
Craig Topper
9204074598 Change type profile for vpermv back to using operand type for the mask argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154798 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 06:43:40 +00:00
Craig Topper
7e9f7fbc11 Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 06:26:15 +00:00
Craig Topper
8325c11d47 Merge vpermps/vpermd and vpermpd/vpermq SD nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 00:41:45 +00:00
Craig Topper
ca9ee66e36 Fix SDTypeProfile for vpermps. The mask operand should be v8i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154781 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 00:12:20 +00:00
Craig Topper
095c528f30 Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154780 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 23:48:57 +00:00
Craig Topper
2cb1e9dc7d Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154778 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 22:43:31 +00:00
Nadav Rotem
f16af0a053 Fix PR12529. The Vxx family of instructions are only supported by AVX. 
Use non-vex instructions for SSE4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 19:36:44 +00:00
Benjamin Kramer
362a05a635 Wire up support for diagnostic ranges in the ARMAsmParser. 
As an example, attach range info to the "invalid instruction" message:

$ clang -arch arm -c asm.c
asm.c:2:11: error: invalid instruction
  __asm__("foo r0");
          ^
<inline asm>:1:2: note: instantiated into assembly here
        foo r0
        ^~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154765 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 17:04:27 +00:00
Elena Demikhovsky
73c504af9d Added VPERM optimization for AVX2 shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 11:18:59 +00:00
NAKAMURA Takumi
8a81df1b7f HexagonCopyToCombine.cpp: Silence two warnings, -Wunused-variable, with -Asserts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154759 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 05:33:43 +00:00
NAKAMURA Takumi
8c67cf44c5 Target/Hexagon: Tweak to fix msvc build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154758 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 05:09:09 +00:00
Richard Smith
42fc29e717 Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ~*x & y. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154705 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 22:47:00 +00:00
Sirish Pande
3423132f2e Remove iostream from New Value Jump. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154703 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 21:01:35 +00:00
Sirish Pande
8800cada20 Add support for Hexagon Architectural feature, New Value Jump. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154696 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 20:22:31 +00:00
Sirish Pande
05a2fea6a5 Pass to replace tranfer/copy instructions into combine instruction where possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154695 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 20:22:19 +00:00
Evan Cheng
7ece9539c2 On Darwin targets, only use vfma etc. if the source use fma() intrinsic explicitly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154689 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 18:59:28 +00:00
Kevin Enderby
6c22695c6d For ARM disassembly only print 32 unsigned bits for the address of branch 
targets so if the branch target has the high bit set it does not get printed as:
	 beq     0xffffffff8008c404


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 18:46:37 +00:00
Craig Topper
7a2e472d52 Silence various build warnings from Hexagon backend that show up in release builds. Mostly converting 'assert(0)' to 'llvm_unreachable' to silence warnings about missing returns. Also fold some variable declarations into asserts to prevent the variables from being unused in release builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154660 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-13 06:38:11 +00:00
Kevin Enderby
2a7d3a9373 Fix a few more places in the ARM disassembler so that branches get 
symbolic operands added when using the C disassembler API.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 23:13:34 +00:00
Ted Kremenek
6bc572ce0e Update CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154622 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 22:15:23 +00:00
Evandro Menezes
cc8002a129 Hexagon: fix CMake error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154620 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 21:44:58 +00:00
Sirish Pande
d1a87a6806 HexagonPacketizer patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154616 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 21:06:38 +00:00
Evan Cheng
f0bcecc0d5 Generalize r153635 to deal with TokenFactor chains; also clean up the logic and fix the tests. rdar://11069732, rdar://11236106 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154604 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 19:14:21 +00:00
Evandro Menezes
e5041e6fa8 Hexagon: enable assembler output through the MC layer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154597 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 17:55:53 +00:00
Benjamin Kramer
503a86b731 Remove README entry obsoleted by register masks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154588 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 12:47:29 +00:00
Craig Topper
bf596c9c61 Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 07:23:00 +00:00
Jim Grosbach
b54efe809f ARM 'adr' fixups don't need the interworking addend tweaking. 
They reference the PC directly, so things work properly that way.

rdar://11231229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154576 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 01:19:35 +00:00
Akira Hatanaka
1cc6333161 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:59:08 +00:00
Akira Hatanaka
c12a6e6b53 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:49:04 +00:00
Kevin Enderby
b318cc16c9 Fixed a case of ARM disassembly getting an assert on a bad encoding 
of a VST instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:40:17 +00:00
Akira Hatanaka
056c51e598 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:13:04 +00:00
Jim Grosbach
1835547ec1 ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction. 
While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11222366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 17:40:18 +00:00
Jim Grosbach
6073b30b05 ARM 'vzip.32 Dd, Dm' is a pseudo-instruction. 
While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11221911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 16:53:25 +00:00
Nadav Rotem
91794872ce remove unused argument 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154494 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 11:05:21 +00:00
Duncan Sands
d6b7b8f49b Add a C binding to the Target and TargetMachine classes to allow for emitting 
binary and assembly. Patch by Carlo Kok.  Emitting was inspired by but not based
on the D llvm bindings. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154493 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 10:25:24 +00:00
Evan Cheng
14b4c03580 Add more fused mul+add/sub patterns. rdar://10139676 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154484 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 06:59:47 +00:00
Nadav Rotem
e611378a6e Reapply 154396 after fixing a test. 
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 06:40:27 +00:00
Evan Cheng
bee78fe5fc Clean up ARM fused multiply + add/sub support some more: rename some isel 
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 05:33:07 +00:00
Evan Cheng
92c904539a Match (fneg (fma) to vfnma. rdar://10139676 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154469 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 01:21:25 +00:00
Charles Davis
0d82fe77f2 Add retw and lretw instructions. Also, fix Intel syntax parsing for all 
ret instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 01:10:53 +00:00
Kevin Enderby
a69da35c12 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case 
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 00:25:40 +00:00
Jim Grosbach
a5378ebe78 ARM add missing Thumb1 two-operand aliases for shift-by-immediate. 
rdar://11222742

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 00:15:16 +00:00
Evan Cheng
82509e5c62 Fix a number of problems with ARM fused multiply add/subtract instructions. 
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 00:13:00 +00:00
Evan Cheng
3aef2ff514 Handle llvm.fma.* intrinsics. rdar://10914096 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154439 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 21:40:28 +00:00