Craig Topper
4e02f23de2
Prune some includes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:54:11 +00:00
Kevin Enderby
9f2e160f7a
Fix assembling ARM vst2 instructions with double-spaced registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20 17:41:51 +00:00
Jim Grosbach
ceee984302
ARM assembly, accept optional '#' on lane index number.
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rdar://11057160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19 20:39:53 +00:00
Jim Grosbach
be7cf2b377
ARM ldm/stm register lists can be out of order.
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It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 20:48:38 +00:00
Jim Grosbach
89eaa6f554
Remove inadvertant commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 23:00:30 +00:00
Jim Grosbach
b84ad4aa7d
ARM case-insensitive checking for APSR_nzcv.
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rdar://11056591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 21:34:14 +00:00
Jim Grosbach
6357caec78
ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
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rdar://11056647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 20:48:18 +00:00
Jim Grosbach
4d0983a4d7
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:10:38 +00:00
Jim Grosbach
c0fc450f07
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 22:01:44 +00:00
Jim Grosbach
c3384c93c0
ARM Refactor VLD/VST spaced pair instructions.
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Use the new composite physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 21:43:40 +00:00
Jim Grosbach
af9f4bc752
ARM Remove a bit of dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 21:09:58 +00:00
Jim Grosbach
28f08c93e7
ARM refactor away a bunch of VLD/VST pseudo instructions.
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:33:30 +00:00
Craig Topper
bc2198133a
Convert assert(0) to llvm_unreachable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 02:50:20 +00:00
Jim Grosbach
24dda21705
Tidy up. One more return type mismatch fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 23:51:09 +00:00
Jim Grosbach
42e6bd38e0
Keep source information, if available, around for ARM Fixups.
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Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 23:20:15 +00:00
Jim Grosbach
ef4d3ebe2a
Tidy up. Fix mismatched return types for error handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 15:56:45 +00:00
Jim Grosbach
74423e32ce
ARM assemly parsing and validation of IT instruction.
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"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 19:52:01 +00:00
Jim Grosbach
a57a36abe7
NEON VLD4(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 00:01:08 +00:00
Jim Grosbach
5e59f7e15e
NEON VLD3(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 23:47:04 +00:00
Jim Grosbach
88a54de799
NEON VST4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:53:13 +00:00
Jim Grosbach
e983a134e7
NEON VLD4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:25 +00:00
Jim Grosbach
539aab771f
NEON VST4(multiple 4 element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:58:13 +00:00
Jim Grosbach
8abe7e3364
NEON VLD4(multiple 4 element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:43:17 +00:00
Jim Grosbach
7945eade3d
Tidy up. Remove some vertical space for readability.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:43:12 +00:00
Jim Grosbach
4adb182342
NEON VST3(single element from one lane) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:07:41 +00:00
Jim Grosbach
d7433e2873
NEON VST3(multiple 3-element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:45:44 +00:00
Jim Grosbach
c387fc66bd
NEON VLD3(multiple 3-element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:20:46 +00:00
Jim Grosbach
3a678af71d
NEON VLD3 lane-indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:53:26 +00:00
Jim Grosbach
8b31f95bdd
Simplify some NEON assembly pseudo definitions.
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Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
Jim Grosbach
12a8863828
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 00:07:56 +00:00
David Blaikie
4d6ccb5f68
More dead code removal (using -Wunreachable-code)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Jim Grosbach
51222d1551
NEON use vmov.i32 to splat some f32 values into vectors.
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For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 18:09:51 +00:00
Jim Grosbach
ae69f703d5
ARM assembly diagnostic caret in better position for FPImm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 02:47:30 +00:00
Jim Grosbach
0b4c673886
Thumb2 alternate syntax for LDR(literal) and friends.
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Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:46:46 +00:00
David Blaikie
2dd674fdce
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
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(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 23:24:27 +00:00
Matt Beaumont-Gay
19055cc271
Fix malformed assert.
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If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 19:03:59 +00:00
Jim Grosbach
4050bc4cab
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:19:05 +00:00
Jim Grosbach
21bcca81f4
Tidy up. Use predicate function a bit more liberally.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:02:35 +00:00
Jim Grosbach
1aa149f5ac
ARM pre-UAL aliases. fcmp[sd].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:20:45 +00:00
Jim Grosbach
8d9550bde9
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 18:04:04 +00:00
Jim Grosbach
de626ad872
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:37:00 +00:00
Jim Grosbach
18c8d12dea
Tidy up. Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:17:10 +00:00
Jim Grosbach
f1a88fc474
Nuke invalid comment from copy/paste.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:04:50 +00:00
Jim Grosbach
de4d83943a
ARM asm parser should be more lenient w/ .thumb_func directive.
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Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 22:30:16 +00:00
Jim Grosbach
520dc78d92
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 21:04:19 +00:00
Jim Grosbach
2cc5cda464
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:54:00 +00:00
Jim Grosbach
c931325d99
ARM assembly parsing allows constant expressions for lane indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Jim Grosbach
aee718beac
ARM .req register name aliases are case insensitive, just like regnames.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:11:00 +00:00
Jim Grosbach
3cbe43fe69
Move comment to appropriate place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:26:38 +00:00