Commit Graph

77910 Commits

Author SHA1 Message Date
Hal Finkel
8faeecead0 Revert "r232027 - Add infrastructure for support of multiple memory constraints"
This (r232027) has caused PR22883; so it seems those bits might be used by
something else after all. Reverting until we can figure out what else to do.

Original commit message:

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232093 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 20:09:39 +00:00
Quentin Colombet
be45e0e669 [X86] Fix a regression introduced by r223641.
The permps and permd instructions have their operands swapped compared to the
intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP
category.

I did not create a new category for those two, as they are the only one AFAICT
in that case.

<rdar://problem/20108262>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232085 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 19:34:12 +00:00
Eric Christopher
63fb193745 Fix comment formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232076 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 18:23:01 +00:00
Eric Christopher
f516a66bdd Remove the need to cache the subtarget in the X86 TargetRegisterInfo
classes. Use a Triple instead and simplify a lot of the querying
logic to use lookups on the Triple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232071 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 17:54:19 +00:00
Krzysztof Parzyszek
7b110fe366 Remove unused complex patterns for addressing modes on Hexagon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232057 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 16:44:50 +00:00
Sanjay Patel
320572f378 make an array of constants explicitly const
Suggested by Craig Topper in D8184.

This goes with r232047.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232056 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 16:29:58 +00:00
Sanjay Patel
656ef652cc IRBuilder: add a CreateShuffleVector function that takes an ArrayRef of int
This is a convenience function to ease mask creation of ShuffleVectors
in AutoUpgrade and other places.

Differential Revision: http://reviews.llvm.org/D8184



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232047 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 15:27:07 +00:00
Andrea Di Biagio
be9322ae7c [X86] Fix wrong target specific combine on SETCC nodes.
Part of the folding logic implemented by function 'PerformISDSETCCCombine'
only worked under the assumption that the condition code in input could have
been either SETNE or SETEQ.
Unfortunately that assumption was incorrect, and in some cases the algorithm
ended up incorrectly folding SETCC nodes.

The incorrect folding only affected SETCC dag nodes where:
 - one of the operands was a build_vector of all zeroes;
 - the other operand was a SIGN_EXTEND from a vector of MVT:i1 elements;
 - the condition code was neither SETNE nor SETEQ.

Example:
  (setcc (v4i32 (sign_extend v4i1:%A)), (v4i32 VectorOfAllZeroes), setge)

Before this patch, the entire dag node sequence from the example was
incorrectly folded to node %A.

With this patch, the dag node sequence is folded to a
  (xor %A, (v4i1 VectorOfAllOnes)).

Added test setcc-combine.ll.

Thanks to Greg Bedwell for spotting this issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232046 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 15:16:58 +00:00
Sanjay Patel
b4c1547749 [X86, AVX] replace vextractf128 intrinsics with generic shuffles
Now that we've replaced the vinsertf128 intrinsics, 
do the same for their extract twins.

This is very much like D8086 (checked in at r231794):
We want to replace as much custom x86 shuffling via intrinsics
as possible because pushing the code down the generic shuffle
optimization path allows for better codegen and less complexity
in LLVM.

This is also the LLVM sibling to the cfe D8275 patch.

Differential Revision: http://reviews.llvm.org/D8276



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232045 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 15:15:19 +00:00
Aaron Ballman
e6a494a4bc Silencing an "enumeral and non-enumeral type in conditional expression" warning; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232035 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 13:24:06 +00:00
Daniel Sanders
67f6425792 Add infrastructure for support of multiple memory constraints.
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8171


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232027 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 11:00:48 +00:00
Elena Demikhovsky
3209a40889 AVX-512: Added encoding tests for VPROR, VPROL instructions,
fixed opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232018 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 07:28:41 +00:00
Eric Christopher
257ea92cdf Remove some unnecessary forward declarations and put a couple more
where they're supposed to reside.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232014 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 06:07:16 +00:00
Eric Christopher
013ed4aa69 Remove the need to cache the subtarget in the Sparc TargetRegisterInfo
classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232013 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 05:55:26 +00:00
Eric Christopher
ae02704ac7 Remove the need to cache the subtarget in the Mips TargetRegisterInfo
classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232012 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 05:43:57 +00:00
Kevin Qin
a56999c5de Reapply 'Run LICM pass after loop unrolling pass.'
It's firstly committed at r231630, and reverted at r231635.

Function pass InstructionSimplifier is inserted as barrier to
make sure loop unroll pass won't affect on LICM pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232011 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 05:36:01 +00:00
Eric Christopher
d86e30a88e Remove the need to cache the subtarget in the ARM TargetRegisterInfo
classes. Replace the frame pointer initialization with a static function
that'll look it up via the subtarget on the MachineFunction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232010 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 05:12:31 +00:00
Eric Christopher
6bfa6d9c08 Remove the need to cache the subtarget in the AArch64 TargetRegisterInfo
classes. Replace it with a cache to the Triple and use that
where applicable at the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232005 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 02:04:46 +00:00
Jingyue Wu
3ea0adcdd5 [NVPTXAsmPrinter] do not print .align on function headers
Summary:
PTX does not allow .align directives on function headers.

Fixes PR21551.

Test Plan: test/Codegen/NVPTX/function-align.ll

Reviewers: eliben, jholewinski

Reviewed By: eliben, jholewinski

Subscribers: llvm-commits, eliben, jpienaar, jholewinski

Differential Revision: http://reviews.llvm.org/D8274

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232004 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 01:50:30 +00:00
Reid Kleckner
b2d414391a Make llvm.eh.actions an intrinsic and add docs for it
These docs *don't* match the way WinEHPrepare uses them yet, and
verifier support isn't implemented either. The implementation will come
after the documentation text is reviewed and agreed upon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232003 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 01:45:37 +00:00
Eric Christopher
e4a40f7a1c Remove the need to cache the subtarget in the PowerPC TargetRegisterInfo
classes. Replace it with a cache to the TargetMachine and use that
where applicable at the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232002 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 01:42:51 +00:00
Krzysztof Parzyszek
55d4acbaf2 Fix build break introduced in r231992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231996 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 00:49:13 +00:00
Reid Kleckner
7dedaabcae Stop calling DwarfEHPrepare from WinEHPrepare
Instead, run both EH preparation passes, and have them both ignore
functions with unrecognized EH personalities. Pass delegation involved
some hacky code for creating an AnalysisResolver that we don't need now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231995 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 00:36:20 +00:00
Krzysztof Parzyszek
9a062b62a7 Eliminate constant-extender profitability checks from Hexagon isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231992 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 00:19:59 +00:00
Mehdi Amini
ceb9150268 Move the DataLayout to the generic TargetMachine, making it mandatory.
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.

Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.

The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.

Test Plan: clang+llvm ninja check-all

Reviewers: echristo

Subscribers: jfb, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8243

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 00:07:24 +00:00
Reid Kleckner
d24c2c8cdf Fix some clang warnings in WinEHPrepare
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231985 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 23:39:36 +00:00
Reid Kleckner
70992ac969 Handle big index in getelementptr instruction
CodeGen incorrectly ignores (assert from APInt) constant index bigger
than 2^64 in getelementptr instruction. This is a test and fix for that.

Patch by Paweł Bylica!

Reviewed By: rnk

Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits

Differential Revision: http://reviews.llvm.org/D8219

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231984 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 23:36:10 +00:00
Hal Finkel
5127011d3a [PowerPC] Remove canFoldAsLoad from instruction definitions
The PowerPC backend had a number of loads that were marked as canFoldAsLoad
(and I'm partially at fault here for copying around the relevant line of
TableGen definitions without really looking at what it meant). This is not
right; PPC (non-memory) instructions don't support direct memory operands, and
so there is nothing a 'foldable' instruction could be folded into.

Noticed by inspection, no test case.

The one thing we might lose by doing this is ability to fold some loads into
stackmap/patchpoint pseudo-instructions. However, this was untested, and would
not obviously have worked for extending loads, and I'd rather re-add support
for that once it can be tested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231982 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 23:28:38 +00:00
Andrew Kaylor
1134ac4a0f Extended support for native Windows C++ EH outlining
Differential Review: http://reviews.llvm.org/D7886



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231981 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 23:22:06 +00:00
Eric Christopher
fba5b65942 Remove useMachineScheduler and replace it with subtarget options
that control, individually, all of the disparate things it was
controlling.

At the same time move a FIXME in the Hexagon port to a new
subtarget function that will enable a user of the machine
scheduler to avoid using the source scheduler for pre-RA-scheduling.
The FIXME would have this removed, but involves either testcase
changes or adding -pre-RA-sched=source to a few testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231980 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 22:56:10 +00:00
Eric Christopher
85aa6fd741 Have getCallPreservedMask and getThisCallPreservedMask take a
MachineFunction argument so that we can grab subtarget specific
features off of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231979 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 22:42:13 +00:00
Eric Christopher
4bf95b38b2 One more getCalleeSavedRegs prototype with nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231977 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 22:24:37 +00:00
Eric Christopher
5233c26b6b Have getCalleeSavedRegs take a non-null MachineFunction all the
time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231970 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 21:41:28 +00:00
Pete Cooper
1ed57f698d Constify AArch64CollectLOH.cpp. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231969 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 21:40:25 +00:00
Jozef Kolek
a2b4e9a30e [mips][microMIPS] Make usage of NOT16 by code generator
Differential Revision: http://reviews.llvm.org/D7748


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231963 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 20:28:31 +00:00
Rafael Espindola
0c78583bf6 Put jump tables in unique sections on COFF.
If a function is going in an unique section (because of -ffunction-sections
for example), putting a jump table in .rodata will keep .rodata alive and
that will keep alive any other function that also has a jump table.

Instead, put the jump table in a unique section that is associated with the
function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231961 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 19:58:37 +00:00
Tim Northover
52f83a9ab3 ARM: simplify and extend byval handling
The main issue being fixed here is that APCS targets handling a "byval align N"
parameter with N > 4 were miscounting what objects were where on the stack,
leading to FrameLowering setting the frame pointer incorrectly and clobbering
the stack.

But byval handling had grown over many years, and had multiple layers of cruft
trying to compensate for each other and calculate padding correctly. This only
really needs to be done once, in the HandleByVal function. Elsewhere should
just do what it's told by that call.

I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits
byvals with the correct C ABI alignment), which simplified HandleByVal.

rdar://20095672

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231959 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 18:54:22 +00:00
Eric Christopher
ca75f1df99 Remove the need to cache the subtarget in the R600 TargetRegisterInfo
classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231954 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 18:43:21 +00:00
Eric Christopher
138fe781d2 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231951 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 18:34:58 +00:00
David Majnemer
9c2d178707 InstCombine: Don't fold call bitcast into args if callee is byval
This fixes a bug reported here:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150309/265341.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231948 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 18:03:05 +00:00
Kit Barton
c5860523be Updated with list of possible improvements we are tracking internally
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231946 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 17:43:43 +00:00
Juergen Ributzka
9814f7b92c Add the "vbroadcasti128" instruction back.
This is a follow-up to r231182. This adds the "vbroadcasti128" instruction
back, but without the intrinsic mapping. Also add a test to check the
instriction encoding.

This is related to rdar://problem/18742778.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231945 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 17:29:03 +00:00
Derek Schuff
87e6561f34 Make NaCl's use of .init_array for static constructors match Linux
Summary:
The generic ELF TargetObjectFile defaults to .ctors, but Linux's
defaults to .init_array by calling InitializeELF with the value of
UseInitArray from TargetMachine. Make NaCl's behavior match.

Reviewers: jvoung
Differential Revision: http://reviews.llvm.org/D8240

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231934 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 16:16:09 +00:00
Benjamin Kramer
2175eac141 Wrap in __MINGW32__ to avoid warnings from msvc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231933 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 16:09:02 +00:00
Benjamin Kramer
e513fc118d Add missing namespace specifier for MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 15:53:24 +00:00
Benjamin Kramer
20f78d477e RtlCaptureContext is absent from the mingw32 headers, provide a prototype.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231929 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 15:41:15 +00:00
Sanjay Patel
c2e4231627 Inliner should not add callgraph edges for intrinsic calls (PR22857)
The CallGraphNode function "addCalledFunction()" asserts that edges are not to intrinsics.

This patch makes sure that the Inliner does not add such an edge to the callgraph.

Fix for clang crash by assertion: https://llvm.org/bugs/show_bug.cgi?id=22857

Differential Revision: http://reviews.llvm.org/D8231



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231927 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 15:12:32 +00:00
Elena Demikhovsky
13cc6f2b6e AVX-512: Added SKX forms of shift instructions.
Added rotation instructions, encoding only.
Added encoding tests for all these forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231916 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 10:25:42 +00:00
Owen Anderson
1b3b8e5be8 Fix another verifier crash where a GC intrinsic would look at the internals of another intrinsic in order to verify itself.
This causes a crash if the referenced intrinsic was malformed.  In this case, we
would already have reported an error on the referenced intrinsic, but then
crashed on the second one when it tried to introspect the first without
error checking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231910 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 06:57:30 +00:00
Rafael Espindola
a5415bcc57 Don't print labels that on ELF are never used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231904 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-11 04:20:31 +00:00