Commit Graph

79660 Commits

Author SHA1 Message Date
Jim Grosbach
93391348dc RuntimeDyld alignment adjustment from MachO file.
The MachO file stores section alignment as log2(alignment-in-bytes). The
allocation routines want the raw alignment-in-bytes value, so adjust
for that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 00:21:53 +00:00
Jim Grosbach
12a8863828 Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21 00:07:56 +00:00
Jakob Stoklund Olesen
4888d5e98c Delete an unused member variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:48:59 +00:00
Jim Grosbach
b442d7c6bf Fix inverted condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:44:03 +00:00
Devang Patel
1aea430b88 Intel syntax: Robustify register parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:32:05 +00:00
Jakob Stoklund Olesen
a3c4ca9c7b Support register masks in MachineLICM.
Only PostRA LICM is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:27:12 +00:00
Jakob Stoklund Olesen
6b88c180da Handle register masks in DeadMachineInstructionElim.
Don't track live physregs that are clobbered by a register mask operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:27:09 +00:00
David Blaikie
4d6ccb5f68 More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Andrew Trick
0041d4d447 Handle a corner case with IV chain collection with bailout instead of assert.
Fixes PR11783: bad cast to AddRecExpr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:23:40 +00:00
Andrew Trick
a44919ef45 Test case comments missing from my previous checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:27 +00:00
Devang Patel
fdd3b30151 Intel syntax: Parse ... PTR [-8]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:14:06 +00:00
Bob Wilson
1e9ccd68d4 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 20:59:56 +00:00
Jim Grosbach
b1320cb381 TblGen diagnostic for mismatched template instantiation.
Providing a template argment to a non-templatized class was crashing
tblgen. Add a diagnostic.

For example,
$ cat bug.td
class A;

def B : A<0> {
}
$ llvm-tblgen bug.td
bug.td:3:11: error: template argument provided to non-template class
def B : A<0> {
          ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 20:02:39 +00:00
Jim Grosbach
6d56730ab8 VST2 four-register w/ update pseudos for fixed/register update.
rdar://10724489

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 19:16:00 +00:00
Jim Grosbach
51222d1551 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 18:09:51 +00:00
Benjamin Kramer
88e900808a Don't use my favorite C++11 feature (comma at end of enum).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148555 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 18:08:30 +00:00
Kostya Serebryany
164b86b439 Extend Attributes to 64 bits
Problem: LLVM needs more function attributes than currently available (32 bits).
One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc).

Solution:
- extend the Attributes from 32 bits to 64-bits
- wrap the object into a class so that unsigned is never erroneously used instead
- change "unsigned" to "Attributes" throughout the code, including one place in clang.
- the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking.
- the class has "safe operator bool()" to support the common idiom:  if (Attributes attr = getAttrs()) useAttrs(attr);
- The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls
- Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work.
- Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit.

Tested:
"make check" on Linux (32-bit and 64-bit) and Mac (10.6)
built/run spec CPU 2006 on Linux with clang -O2.


This change will break clang build in lib/CodeGen/CGCall.cpp.
The following patch will fix it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 17:56:17 +00:00
Benjamin Kramer
3feccbaaee Protect SmallVectorImpl's constructor and a few other methods that aren't meant to be public.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 16:39:46 +00:00
Benjamin Kramer
eb9fa666f9 Add missing breaks to switch.
Found by the clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 14:42:37 +00:00
Benjamin Kramer
263109d822 Remove a bunch of unused variable assignments.
Found by the clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 14:42:32 +00:00
Benjamin Kramer
07df1b4d1a Remove obviously invalid early exit that prevented analyzing ConstantAggregateZeros.
Found by the clang static analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 14:42:25 +00:00
Rafael Espindola
ace4f2b0d4 Don't use -fvisibility-inlines-hidden on mingw to try to avoid a lot of
warnings from gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148539 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 13:10:10 +00:00
Craig Topper
8f35c13842 Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 09:29:03 +00:00
Nick Lewycky
38b6d9dd22 Fix CountCodeReductionForAlloca to more accurately represent what SROA can and
can't handle. Also don't produce non-zero results for things which won't be
transformed by SROA at all just because we saw the loads/stores before we saw
the use of the address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 08:35:20 +00:00
Andrew Trick
b5c26ef9da SCEVExpander fixes. Affects LSR and indvars.
LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes:

- Always used properlyDominates to check safe code hoisting.

- The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point.

- LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions.

- Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point.

Fixes PR11783: SCEVExpander assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 07:41:13 +00:00
Craig Topper
0e2037ba2b Add support for selecting 256-bit PALIGNR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 05:53:00 +00:00
Rafael Espindola
b28885057e cmake: pass -fvisibility-inlines-hidden if it is supported. In a
Release+Asserts build with -DBUILD_SHARED_LIBS=ON, the install
directory goes from 72MB to 70MB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 04:07:48 +00:00
Eli Friedman
a48678332b Remove a low-quality test which was failing on Windows; test/CodeGen/X86/sret.ll is a better test for the relevant behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 02:06:40 +00:00
Bill Wendling
b618ea5ff9 When lowering the 'resume' instruction, look to see if we can eliminate the
'insertvalue' instructions that recreate the structure returned by the
'landingpad' instruction. Because the 'insertvalue' instruction isn't supported
by FastISel, this can save a bit of time during -O0 compilation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 00:53:28 +00:00
Eli Friedman
9a2478ac1a Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 00:05:46 +00:00
Chad Rosier
f46fbade8a Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148497 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 21:50:08 +00:00
Benjamin Kramer
e545ee20f1 Silence warnings about mixing enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 21:11:13 +00:00
Owen Anderson
27ff6b5e2b Add a dump() implementation for sub-instruction MCOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 19:32:20 +00:00
Owen Anderson
7b672fe03b Add a new form of MCOperand, for representing sub-instructions. This is intended for supporting bundles through the MC layer, rather than lowering them pre-MC as we currently do for Thumb2 IT blocks. Since these sub-instruction operands hold pointers to the sub-instructions, it is the responsibility of the target's AsmPrinter to provide storage for them for the duration of the EmitInstruction() call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148492 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 19:24:37 +00:00
Dan Gohman
0cdece4389 Set the "tail" flag on pattern-matched objc_storeStrong calls.
rdar://10531041.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148490 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 19:14:36 +00:00
Devang Patel
a951f77ca3 Post process 'and', 'sub' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:40:55 +00:00
Nick Lewycky
f460bf8cd8 Actually, this code handles wrapped sets just fine. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:19:42 +00:00
Devang Patel
e60540f380 Intel syntax: There is no need to create unary expr for simple negative displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 17:53:25 +00:00
Evgeniy Stepanov
73dd8bbce3 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 12:53:06 +00:00
Craig Topper
40385c8104 Folding table additions and fixes for AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148467 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:50:38 +00:00
Craig Topper
1a7700a3fa Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:19:12 +00:00
Evan Cheng
ef2887d348 More bundle related API additions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 07:47:03 +00:00
Evan Cheng
3f9c251e40 Rewriter should definitly rewrite instructions inside bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148464 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 07:46:36 +00:00
Chris Lattner
46ada15d42 Introduce a new MutableArrayRef class, which refers to a series of mutable
T's that are consequtively in memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 06:34:52 +00:00
Evan Cheng
a2e435cd23 Enhance finalizeBundle to return end of bundle iterator because it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 06:13:10 +00:00
Jim Grosbach
ae69f703d5 ARM assembly diagnostic caret in better position for FPImm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 02:47:30 +00:00
Jim Grosbach
9363c58dc2 Thumb2 relaxation for tADR to t2ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 02:09:38 +00:00
Jim Grosbach
d26bad079d Add comment and fix range check in condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 01:50:30 +00:00