Commit Graph

263 Commits

Author SHA1 Message Date
Craig Topper
61f49542d7 [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 04:15:57 +00:00
Owen Anderson
13146c7e3b Add initial support for the convergent attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238264 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 23:48:40 +00:00
James Y Knight
aeda490976 Fix tablegen's PrintFatalError function to run registered file
cleanups.

Also, change code in tablegen which printed a message and then called
"exit(1)" to use PrintFatalError, instead.

This fixes instances where an empty output file was left behind after
a failed tablegen invocation, which would confuse subsequent ninja
runs into not attempting to rebuild.

Differential Revision: http://reviews.llvm.org/D9608

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237058 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-11 22:17:13 +00:00
Kit Barton
1e3da044d8 Add support for v1i128 type.
The v1i128 type is needed for the quadword add/substract instructions introduced
in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128
are to be passed in a single vector register, while parameters of type i128 are
passed in pairs of GPRs. Thus, it is necessary to be able to differentiate
between v1i128 and i128 in LLVM.

http://reviews.llvm.org/D8564


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235198 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-17 16:11:05 +00:00
Ramkumar Ramachandra
230796b278 Intrinsics: introduce llvm_any_ty aka ValueType Any
Specifically, gc.result benefits from this greatly. Instead of:

gc.result.int.*
gc.result.float.*
gc.result.ptr.*
...

We now have a gc.result.* that can specialize to literally any type.

Differential Revision: http://reviews.llvm.org/D7020

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226857 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-22 20:14:38 +00:00
Reid Kleckner
221a7075cf Add the llvm.frameallocate and llvm.recoverframeallocation intrinsics
These intrinsics allow multiple functions to share a single stack
allocation from one function's call frame. The function with the
allocation may only perform one allocation, and it must be in the entry
block.

Functions accessing the allocation call llvm.recoverframeallocation with
the function whose frame they are accessing and a frame pointer from an
active call frame of that function.

These intrinsics are very difficult to inline correctly, so the
intention is that they be introduced rarely, or at least very late
during EH preparation.

Reviewers: echristo, andrew.w.kaylor

Differential Revision: http://reviews.llvm.org/D6493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225746 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-13 00:48:10 +00:00
Elena Demikhovsky
b31322328a Masked Load/Store - Changed the order of parameters in intrinsics.
No functional changes.
The documentation is coming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224829 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-25 07:49:20 +00:00
Craig Topper
f492c9e612 Use unique_ptr instead of DeleteContainerSeconds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223918 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-10 06:18:57 +00:00
Craig Topper
d5578c8ba3 Use range-based for loops. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223762 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 08:05:51 +00:00
Elena Demikhovsky
73ae1df82c Masked Load / Store Intrinsics - the CodeGen part.
I'm recommiting the codegen part of the patch.
The vectorizer part will be send to review again.

Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-04 09:40:44 +00:00
David Blaikie
7a16f34aa6 Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead of vector<CodeGenRegisterClass*>
This complicates a few algorithms due to not having random access, but
not by a huge degree I don't think (open to debate/design
discussion/etc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223261 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-03 19:58:45 +00:00
David Blaikie
89036eb44c Range-for some stuff related to RegClasses, and comment cases where range-for isn't suitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223260 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-03 19:58:41 +00:00
Philip Reames
78cc6fcb01 [Statepoints 2/4] Statepoint infrastructure for garbage collection: MI & x86-64 Backend
This is the second patch in a small series.  This patch contains the MachineInstruction and x86-64 backend pieces required to lower Statepoints.  It does not include the code to actually generate the STATEPOINT machine instruction and as a result, the entire patch is currently dead code.  I will be submitting the SelectionDAG parts within the next 24-48 hours.  Since those pieces are by far the most complicated, I wanted to minimize the size of that patch.  That patch will include the tests which exercise the functionality in this patch.  The entire series can be seen as one combined whole in http://reviews.llvm.org/D5683.

The STATEPOINT psuedo node is generated after all gc values are explicitly spilled to stack slots.  The purpose of this node is to wrap an actual call instruction while recording the spill locations of the meta arguments used for garbage collection and other purposes.  The STATEPOINT is modeled as modifing all of those locations to prevent backend optimizations from forwarding the value from before the STATEPOINT to after the STATEPOINT.  (Doing so would break relocation semantics for collectors which wish to relocate roots.)

The implementation of STATEPOINT is closely modeled on PATCHPOINT.  Eventually, much of the code in this patch will be removed.  The long term plan is to merge the functionality provided by statepoints and patchpoints.  Merging their implementations in the backend is likely to be a good starting point.

Reviewed by: atrick, ributzka



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-01 22:52:56 +00:00
Duncan P. N. Exon Smith
54786a0936 Revert "Masked Vector Load and Store Intrinsics."
This reverts commit r222632 (and follow-up r222636), which caused a host
of LNT failures on an internal bot.  I'll respond to the commit on the
list with a reproduction of one of the failures.

Conflicts:
	lib/Target/X86/X86TargetTransformInfo.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222936 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-28 21:29:14 +00:00
Craig Topper
0c83952c2e Use unique_ptr to simplify deletion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222929 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-28 20:30:37 +00:00
Elena Demikhovsky
ae1ae2c3a1 Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 08:07:43 +00:00
Akira Hatanaka
0651a556fe [stack protector] Fix a potential security bug in stack protector where the
address of the stack guard was being spilled to the stack.

Previously the address of the stack guard would get spilled to the stack if it
was impossible to keep it in a register. This patch introduces a new target
independent node and pseudo instruction which gets expanded post-RA to a
sequence of instructions that load the stack guard value. Register allocator
can now just remat the value when it can't keep it in a register. 

<rdar://problem/12475629>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213967 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 19:31:34 +00:00
Saleem Abdulrasool
bb5f6229f4 TableGen: introduce support for MSBuiltin
Add MSBuiltin which is similar in vein to GCCBuiltin.  This allows for adding
intrinsics for Microsoft compatibility to individual instructions.  This is
needed to permit the creation of ARM specific MSVC extensions.

This is not currently in use, and requires an associated change in clang to
enable use of the intrinsics defined by this new class.  This merely sets the
LLVM portion of the infrastructure in place to permit the use of this
functionality.  A separate set of changes will enable the new intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-04 18:42:25 +00:00
Craig Topper
095734c578 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 07:20:03 +00:00
Benjamin Kramer
abe43b546b tblgen: Twinify PrintFatalError.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 17:17:15 +00:00
Tim Northover
b7de4288bc Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)
These are used in the ARM backends to aid type-checking on patterns involving
intrinsics. By making sure one argument is an extended/truncated version of
another.

However, there's no reason to limit them to just vectors types. For example
AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an
intrinsic taking an i64 and returning an i32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205003 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 12:31:39 +00:00
Eli Bendersky
21354ec60d Expose "noduplicate" attribute as a property for intrinsics.
The "noduplicate" function attribute exists to prevent certain optimizations
from duplicating calls to the function. This is important on platforms where
certain function call duplications are unsafe (for example execution barriers
for CUDA and OpenCL).

This patch makes it possible to specify intrinsics as "noduplicate" and
translates that to the appropriate function attribute.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 23:51:07 +00:00
Rafael Espindola
7d7d99622f Replace PROLOG_LABEL with a new CFI_INSTRUCTION.
The old system was fairly convoluted:
* A temporary label was created.
* A single PROLOG_LABEL was created with it.
* A few MCCFIInstructions were created with the same label.

The semantics were that the cfi instructions were mapped to the PROLOG_LABEL
via the temporary label. The output position was that of the PROLOG_LABEL.
The temporary label itself was used only for doing the mapping.

The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to
one by holding an index into the CFI instructions of this function.

I did consider removing MMI.getFrameInstructions completelly and having
CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non
trivial constructors and destructors and are somewhat big, so the this setup
is probably better.

The net result is that we don't create temporary labels that are never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 06:08:31 +00:00
Rafael Espindola
ec7ab53570 clang-format a bit of code to make the next patch easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 05:32:03 +00:00
Benjamin Kramer
ee5e607355 Now that we have C++11, turn simple functors into lambdas and remove a ton of boilerplate.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 11:47:00 +00:00
Craig Topper
a4f328f68b Delete all of the CodeGenInstructions from CodeGenTarget destructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 06:27:59 +00:00
Craig Topper
7583b60306 Fix a doxygen comment referencing the wrong method name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200825 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 07:21:07 +00:00
Craig Topper
f3474549ba Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200036 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 20:50:47 +00:00
Hal Finkel
af73dfe6f1 Support little-endian encodings in the FixedLenDecoderEmitter
The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-17 22:37:50 +00:00
Andrew Trick
2343e3b228 Lower stackmap intrinsics directly to their target opcode in the DAG builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:18:24 +00:00
Pete Cooper
da750239bd Add v4f16 to supported value types.
This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191870 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 03:29:21 +00:00
Jiangning Liu
477fc628b3 Initial support for Neon scalar instructions.
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-24 02:47:27 +00:00
Jack Carter
0fe3792a2f [Mips][msa] Value types for MSA support.
Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, 
and CodeGenTarget.cpp

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 22:34:26 +00:00
Craig Topper
3c70fcf02b Add 'const' qualifier to some arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 08:02:13 +00:00
Nick Lewycky
dc89737bcd Extend 'readonly' and 'readnone' to work on function arguments as well as
functions. Make the function attributes pass add it to known library functions
and when it can deduce it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 00:29:58 +00:00
Jakob Stoklund Olesen
26369a930c Use ArrayRef<MVT::SimpleValueType> when possible.
Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-17 17:26:09 +00:00
Elena Demikhovsky
94d7ab7da4 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 10:03:57 +00:00
Chandler Carruth
4ffd89fa4d Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 10:37:14 +00:00
Joerg Sonnenberger
61131ab15f Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 20:33:17 +00:00
Micah Villmow
3e9b6db60f Add in new data types that are used by AMDIL/ANL among others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 22:47:07 +00:00
Owen Anderson
d2c699706c Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 23:32:17 +00:00
Nadav Rotem
c05d30601c Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 09:17:37 +00:00
Jakob Stoklund Olesen
f104bf65b9 Add CodeGenTarget::guessInstructionProperties.
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:34:41 +00:00
Andrew Trick
2661b411cc I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 04:00:00 +00:00
Andrew Trick
06495cd7f2 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 03:59:51 +00:00
Chris Lattner
86208903cb rdar://11542750 - llvm.trap should be marked no return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27 23:20:41 +00:00
Jim Grosbach
194f3fa9ea Revert "Emit the SubRegTable with the smallest possible integer type."
This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 17:30:35 +00:00
Benjamin Kramer
b9ace0215d Emit the SubRegTable with the smallest possible integer type.
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:57:08 +00:00
Craig Topper
655b8de7b2 Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 07:21:30 +00:00
Pete Cooper
ddfda5cd16 Added MVT::v2f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 23:14:13 +00:00