Commit Graph

1101 Commits

Author SHA1 Message Date
Evan Cheng
884c70c912 On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size.
e.g.
movl 4(%esp), %eax
addl $4, %eax

is 2 bytes shorter than

movl $4, %eax
addl 4(%esp), %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60139 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-27 00:49:46 +00:00
Evan Cheng
bc7e0f5dd6 Add -march=x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60135 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-27 00:37:06 +00:00
Bill Wendling
e21815f41b Add x86-specific test for add-with-overflow intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60125 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 22:42:19 +00:00
Chris Lattner
ab8b794a78 Turn on my codegen prepare heuristic by default. It doesn't affect
performance in most cases on the Grawp tester, but does speed some 
things up (like shootout/hash by 15%).  This also doesn't impact 
compile time in a noticable way on the Grawp tester.

It also, of course, gets the testcase it was designed for right :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60120 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 22:16:44 +00:00
Chris Lattner
5eecb7f164 This adds in some code (currently disabled unless you pass
-enable-smarter-addr-folding to llc) that gives CGP a better
cost model for when to sink computations into addressing modes.
The basic observation is that sinking increases register 
pressure when part of the addr computation has to be available
for other reasons, such as having a use that is a non-memory
operation.  In cases where it works, it can substantially reduce
register pressure.

This code is currently an overall win on 403.gcc and 255.vortex
(the two things I've been looking at), but there are several 
things I want to do before enabling it by default:

1. This isn't doing any caching of results, so it is much slower 
   than it could be.  It currently slows down release-asserts llc 
   by 1.7% on 176.gcc: 27.12s -> 27.60s.
2. This doesn't think about inline asm memory operands yet.
3. The cost model botches the case when the needed value is live
   across the computation for other reasons.

I'll continue poking at this, and eventually turn it on as llcbeta.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60074 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 02:00:14 +00:00
Chris Lattner
2efbbb38ba Teach CodeGenPrepare to look through Bitcast instructions when attempting to
optimize addressing modes.  This allows us to optimize things like isel-sink2.ll
into:

	movl	4(%esp), %eax
	cmpb	$0, 4(%eax)
	jne	LBB1_2	## F
LBB1_1:	## TB
	movl	$4, %eax
	ret
LBB1_2:	## F
	movzbl	7(%eax), %eax
	ret

instead of:

_test:
	movl	4(%esp), %eax
	cmpb	$0, 4(%eax)
	leal	4(%eax), %eax
	jne	LBB1_2	## F
LBB1_1:	## TB
	movl	$4, %eax
	ret
LBB1_2:	## F
	movzbl	3(%eax), %eax
	ret

This shrinks (e.g.) 403.gcc from 1133510 to 1128345 lines of .s.

Note that the 2008-10-16-SpillerBug.ll testcase is dubious at best, I doubt
it is really testing what it thinks it is.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60068 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 00:26:16 +00:00
Chris Lattner
6d235bb7a0 fix an over-reduced test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60067 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 00:12:08 +00:00
Chris Lattner
d87f570270 this doesn't need EH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60066 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 00:03:26 +00:00
Dan Gohman
21d9003087 Initial support for anti-dependence breaking. Currently this code does not
introduce any new spilling; it just uses unused registers.

Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59999 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-25 00:52:40 +00:00
Owen Anderson
75fa96bb71 Add support for rematerialization in pre-alloc-splitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59587 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-19 04:28:29 +00:00
Lang Hames
1aed723261 Removed 2008-10-17-SpillerBug.ll as it does not provide an accurate test of PR2898.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59431 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-16 23:30:12 +00:00
Lang Hames
684bd46a57 2008-10-17-SpillerBug.ll is currently failing, but this doesn't reflect an actual regression of PR2898. This test should probably be removed. I've XFAILed it for now to keep buildbot quiet while this is considered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59415 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-16 13:11:09 +00:00
Mon P Wang
c7849c22f4 Improved shuffle normalization to avoid using extract/build when we
can extract using different indexes for two vectors. Added a few tests
for vector shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59399 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-16 05:06:27 +00:00
Dan Gohman
d23e0f81bc Remove the FlaggedNodes member from SUnit. Instead of requiring each SUnit
to carry a SmallVector of flagged nodes, just calculate the flagged nodes
dynamically when they are needed.

The local-liveness change is due to a trivial scheduling change where
the scheduler arbitrary decision differently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59273 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 23:24:17 +00:00
Dale Johannesen
e4f309e582 testcase for PR 1779.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59268 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 22:17:10 +00:00
Dale Johannesen
cbf7cf50ec Fix the testb optimization so x86 also bootstraps.
Reenable test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59101 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-12 02:00:35 +00:00
Bill Wendling
d0ab34bf8f Temporarily revert r58979 and related patch. It's causing a failure in X86 bootstrap:
Comparing stages 2 and 3
warning: ./cc1-checksum.o differs
warning: ./cc1obj-checksum.o differs
warning: ./cc1objplus-checksum.o differs
warning: ./cc1plus-checksum.o differs
Bootstrap comparison failure!
./alias.o differs
./alloc-pool.o differs
./attribs.o differs
./bb-reorder.o differs
./bitmap.o differs
./build/errors.o differs
./build/genattrtab.o differs
./build/genautomata.o differs
./build/genemit.o differs
./build/genextract.o differs
...

-bw


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59003 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-10 21:22:06 +00:00
Duncan Sands
a29c13086a When promoting the result of fp_to_uint/fp_to_sint,
inform the optimizers that the result must be zero/
sign extended from the smaller type.  For example,
if a fp to unsigned i16 is promoted to fp to i32,
then we are allowed to assume that the extra 16 bits
are zero (because the result of fp to i16 is undefined
if the result does not fit in an i16).  This is
quite aggressive, but should help the optimizers
produce better code.  This requires correcting a
test which thought that fp_to_uint is some kind
of truncation, which it is not: in the testcase
(which does fp to i1), either the fp value converts
to 0 or 1 or the result is undefined, which is
quite different to truncation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58991 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-10 17:28:30 +00:00
Dale Johannesen
22a8e9e511 Reenable test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58980 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-10 07:30:32 +00:00
Duncan Sands
4d16a0aa58 XFAIL this while waiting for a fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58934 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-09 13:07:47 +00:00
Dale Johannesen
815fb57226 Testcase for testb optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58827 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-07 01:30:18 +00:00
Evan Cheng
b35ed9247a Add more vector move low and zero-extend patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58752 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 06:04:51 +00:00
Dan Gohman
f6503a031e The ANDMask node folds to a constant, and isn't the node that needs to
have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58655 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03 23:43:55 +00:00
Dan Gohman
3a5797d946 Change how extended types are represented in MVTs. Instead of fiddling
bits, use a union of a SimpleValueType enum and a regular Type*.

This increases the size of MVT on 64-bit hosts from 32 bits to 64 bits.
In most cases, this doesn't add significant overhead. There are places
in codegen that use arrays of MVTs, so these are now larger, but
they're small in common cases.

This eliminates restrictions on the size of integer types and vector
types that can be represented in codegen. As the included testcase
demonstrates, it's now possible to codegen very large add operations.
There are still some complications with using very large types. PR2880
is still open so they can't be used as return values on normal targets,
there are no libcalls defined for very large integers so operations
like multiply and divide aren't supported.

This also introduces a minimal tablgen Type library, capable of
handling IntegerType and VectorType. This will allow parts of
TableGen that don't depend on using SimpleValueType values to handle
arbitrary integer and vector types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58623 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03 17:56:27 +00:00
Duncan Sands
5c58a3168f Make VAARG work with x86 long double (which is
10 bytes long, but is passed in 12/16 bytes).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58608 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03 11:51:11 +00:00
Dan Gohman
d17cfbe1ca Use MOVSSmr instead of EXTRACTPSmr in the case of extracting
vector element 0 for a store, as it's smaller and faster.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31 00:57:24 +00:00
Duncan Sands
21c2972f7d Fix PR2977: LegalizeTypes support for expanding
VAARG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58379 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29 14:25:28 +00:00
Evan Cheng
5489893867 - More pre-split fixes: spill slot live interval computation bug; restore point bug.
- If a def is spilt, remember its spill index to allow its reuse.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58375 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29 08:39:34 +00:00
Chris Lattner
4002a1b6f1 Fix a nasty miscompilation of 176.gcc on linux/x86 where we synthesized
a memset using 16-byte XMM stores, but where the stack realignment code
didn't work.  Until it does (PR2962) disable use of xmm regs in memcpy
and memset formation for linux and other targets with insufficiently
aligned stacks.

This is part of PR2888



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58317 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-28 05:49:35 +00:00
Evan Cheng
f62ce370a4 Avoid putting a split past the end of the live range; always shrink wrap live interval in the barrier mbb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58309 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-28 00:47:49 +00:00
Evan Cheng
b3990d5e94 Remove val# defined by a remat'ed def that is now dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58294 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 23:21:01 +00:00
Duncan Sands
7cb07874dc Turn on LegalizeTypes, the new type legalization
codegen infrastructure, by default.  Please report
any breakage to the mailing lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58232 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 08:42:46 +00:00
Evan Cheng
23066288fd For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 07:14:50 +00:00
Evan Cheng
aaf510c932 Do not shrink wrap live interval in a mbb if it's livein any of its successor blocks. The mbb can be revisited again after all of the successors are processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58184 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-26 07:49:03 +00:00
Evan Cheng
79d5b5acae Handle cases where there aren't uses in the barrier mbb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58174 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25 23:49:39 +00:00
Evan Cheng
78dfef771b If val# def is ~0U, meaning it's defined by a PHI, and it's previously split, spill before the barrier because it's impossible to determine if all the defs are spilled in the same spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58129 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25 00:52:41 +00:00
Dale Johannesen
47106ba658 Be kind to non-x86 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58113 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-24 21:20:25 +00:00
Duncan Sands
4047f4a0b4 Fix translateX86CC: if SetCCOpcode is SETULE and
LHS is a foldable load, then LHS and RHS are swapped
and SetCCOpcode is changed to SETUGT.  But the later
code is expecting operands to be the wrong way round
for SETUGT, but they are not in this case, resulting
in an inverted compare.  The solution is to move the
load normalization before the correction for SETUGT.
This bug was tickled by LegalizeTypes which happened
to legalize the testcase slightly differently to
LegalizeDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58092 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-24 13:03:10 +00:00
Evan Cheng
06587497dc Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58068 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-24 02:05:00 +00:00
Dan Gohman
7ea1ca6229 Fix SelectionDAGBuild lowering of Select instructions to
handle first-class aggregate values. Also, fix a bug in
the Ret handling for empty aggregates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57925 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 20:00:42 +00:00
Chris Lattner
7fb501c9cd really fix run line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57889 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:55:19 +00:00
Chris Lattner
0294ac2e9a fix run line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57888 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:54:49 +00:00
Chris Lattner
402135f9e9 remove some unneeded eh generation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57887 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:49:19 +00:00
Dan Gohman
4401361a2f Don't create TargetGlobalAddress nodes with offsets that don't fit
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.

Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57885 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:38:42 +00:00
Dan Gohman
279c22e6da Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:

        ucomisd %xmm1, %xmm0
        setne   %al
        setp    %cl
        orb     %al, %cl
        jne     .LBB4_2

it now emits this:

        ucomisd %xmm1, %xmm0
        jne     .LBB4_2
        jp      .LBB4_2

It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.

To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.

Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:29:32 +00:00
Dan Gohman
3afda6e9d1 When the coalescer is doing rematerializing, have it remove
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.

Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.

These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57872 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:24:31 +00:00
Chris Lattner
01426e1a27 Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts
for strange asm conditions earlier.  In this case, we have a
double being passed in an integer reg class.  Convert to like
sized integer register so that we allocate the right number 
for the class (two i32's for the f64 in this case).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57862 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 00:45:36 +00:00
Dan Gohman
6520e20e4f Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
Evan Cheng
af42fe36ac Fix PR2898. Spiller delete a store for reuse before it knows for sure the reuse happened.
Patch by Lang Hames!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57720 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 20:56:41 +00:00
Chris Lattner
3d0c4c4657 Fix a bug where the x86 backend would reject 64-bit r constraints when
in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57704 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 17:59:52 +00:00
Evan Cheng
6784598895 Fix a very subtle spiller bug: UpdateKills should not forget to track defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57673 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 06:16:07 +00:00
Dan Gohman
63f97201dc Fun x86 encoding tricks: when adding an immediate value of 128,
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 01:33:43 +00:00
Dan Gohman
74feef261a Define patterns for shld and shrd that match immediate
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 01:23:35 +00:00
Dan Gohman
c90a5c2878 Fix this test so it actually runs the grep lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57653 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16 23:57:54 +00:00
Duncan Sands
078ae1e6ee Testcase for PR2762.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57633 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16 08:56:46 +00:00
Evan Cheng
7f04268176 - Add target lowering hooks that specify which setcc conditions are illegal,
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-15 02:05:31 +00:00
Dan Gohman
7b8e96401c When doing the very-late shift-and address-mode optimization,
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.

If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.

This fixes PR2849.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57465 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-13 20:52:04 +00:00
Evan Cheng
195cd3a58d Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57458 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-13 18:35:52 +00:00
Evan Cheng
09fd418106 Add a test case for _Complex passed as a FCA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57456 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-13 18:13:07 +00:00
Chris Lattner
e563bbc312 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-11 22:08:30 +00:00
Dan Gohman
eb0d6abee3 Remove -disable-fast-isel. Use cl::boolOrDefault with -fast-isel
instead.

So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57270 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-07 23:00:56 +00:00
Dan Gohman
00877fc657 Add a testcase for i256 add. i256 isn't fully supported in
codegen right now, but add and subtract work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57260 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-07 20:39:12 +00:00
Anders Carlsson
ae436cecca Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57246 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-07 16:14:11 +00:00
Dale Johannesen
2df5eec2ff Be more precise about which conversions of NaNs
are Inexact.  (These are not Inexact as defined
by IEEE754, but that seems like a reasonable way
to abstract what happens:  information is lost.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57218 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-06 22:59:10 +00:00
Evan Cheng
882cdfde51 Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57210 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-06 21:13:08 +00:00
Anton Korobeynikov
c4e8bec703 Revert r56675 - it breaks unwinding runtime everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57048 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-04 11:09:36 +00:00
Dan Gohman
022b21ff7c Fix a bug in the local allocator's liveness computation where it
was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57039 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-04 00:31:14 +00:00
Dale Johannesen
48c1bc2ace Handle some 64-bit atomics on x86-32, some of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02 18:53:47 +00:00
Dan Gohman
d790a5ceee Fix a think-o in isSafeToMove. This fixes it from thinking that
volatile memory references are safe to move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56948 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02 15:04:30 +00:00
Dan Gohman
0b3baaa7fb Disable fast-isel for this test, as it doesn't emit the same
number of instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56940 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 23:48:35 +00:00
Devang Patel
4ae641f4d1 Remove OptimizeForSize global. Use function attribute optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 23:18:38 +00:00
Dan Gohman
e7aa7baa76 Split this test and move it into target-specific directories.
This fixes failures on configurations that don't have one or the
other targets enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56926 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 19:46:30 +00:00
Dan Gohman
e7891c705c nounwind-ify this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 15:07:14 +00:00
Bill Wendling
ae595dc9da Moved this option to the front-end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56901 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 01:02:18 +00:00
Dan Gohman
70695fee51 Use explicit target-triples to unbreak this test on non-darwin systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56896 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 00:25:38 +00:00
Bill Wendling
6e08738d4b Just don't transform this memset into "bzero" if no-builtin is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56888 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 22:05:33 +00:00
Bill Wendling
fd8ca5a0ef - Initialize "--no-builtin" to "false".
- Testcase for r56885.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56886 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 21:40:30 +00:00
Evan Cheng
dc37786595 Re-apply 56835 along with header file changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56848 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 15:44:16 +00:00
Duncan Sands
46292be362 Revert commit 56835 since it breaks the build.
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56837 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 10:00:30 +00:00
Evan Cheng
d41474d2c0 If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56835 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-30 06:36:58 +00:00
Evan Cheng
d47e0b664f Fix PR2835. Do not change the width of a volatile load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56792 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-29 17:26:18 +00:00
Evan Cheng
184793fc8a Re-apply 56683 with fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-27 01:56:22 +00:00
Evan Cheng
b7a75a5a54 Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56711 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26 23:41:32 +00:00
Bill Wendling
d5d8191b20 Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition  -isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include  -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26 22:10:44 +00:00
Evan Cheng
36a55023c1 Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26 19:48:35 +00:00
Evan Cheng
a67f32abb5 Avoid spilling EBP / RBP twice in the prologue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56675 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26 19:14:21 +00:00
Evan Cheng
4dcc8a373d Prefer movlhps over punpcklqdq, etc. in more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56627 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-25 23:35:16 +00:00
Evan Cheng
0b457f0c3a With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56620 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-25 20:50:48 +00:00
Dale Johannesen
c9c6da61ac Accept 'inreg' attribute on x86 functions as
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0).  Update documentation
to reflect reality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56619 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-25 20:47:45 +00:00
Evan Cheng
ca57f78332 Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56594 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 23:27:55 +00:00
Dale Johannesen
8e3455ba17 Remove SelectionDag early allocation of registers
for earlyclobbers.  Teach Local RA about earlyclobber,
and add some tests for it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56592 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 23:13:09 +00:00
Evan Cheng
da43bcf624 Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 00:05:32 +00:00
Evan Cheng
364091e090 Support x86 specific inline asm modifier 'J'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 23:57:37 +00:00
Arnold Schwaighofer
290ae0398e Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56436 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22 14:50:07 +00:00
Evan Cheng
5e8d9def77 Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-20 01:28:05 +00:00
Evan Cheng
4070e60efe Clean up the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-20 01:26:27 +00:00
Evan Cheng
91a23c8233 No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56378 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-20 00:13:45 +00:00
Dan Gohman
2ff7fd1461 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56371 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 22:16:54 +00:00
Evan Cheng
20580a1cf6 Re-materalized definition instructions may be dead. Whack them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56352 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-19 17:38:47 +00:00
Dale Johannesen
91aac1015e Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 21:13:11 +00:00