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4194 Commits

Author SHA1 Message Date
Bob Wilson
d11c57a937 PR9030: Fix disassembly of ARM "mov pc, lr" instruction. 
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 17:50:30 +00:00
Evan Cheng
c3a20bab75 Fix PLD encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:48:34 +00:00
Kevin Enderby
9e56fb12c5 Changed llvm-mc arm target to give an error if .syntax divided is used. Since 
only .syntax unified is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:22:36 +00:00
Roman Divacky
bf7553210a Introduce virtual ParseRegister method in TargetAsmParser. 
Create override of this method in X86/ARM/MBlaze.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 17:14:22 +00:00
Eric Christopher
4a2b316762 Use the incoming VT not the VT of where we're trying to store to determine 
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124357 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 05:44:56 +00:00
Bill Wendling
8cb415e4c0 Add support for printing out floating point values from the ARM assembly 
parser. The parser will always give us a binary representation of the floating
point number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 20:57:43 +00:00
Bruno Cardoso Lopes
1b10d5be40 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:28:14 +00:00
Bill Wendling
717082b9bd Add needed braces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:06:22 +00:00
Bill Wendling
0f4db7efa1 Revert 124230. It was causing test failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 21:48:36 +00:00
Bill Wendling
261b9c1a35 The floating point value is encoded in its binary form as an Imm. Convert it 
appropriately so that it prints out the decimal representation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 21:27:46 +00:00
Evan Cheng
7cfa656ad8 Don't merge restore with tail call instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 01:28:33 +00:00
Anton Korobeynikov
5899a60d2f Provide correct registers for EH stuff on ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 22:38:45 +00:00
Rafael Espindola
96aa78c8c5 Add support for the --noexecstack option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:55:27 +00:00
Ted Kremenek
584520e8e2 Null initialize a few variables flagged by 
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:05:06 +00:00
Rafael Espindola
1c13026e8f Remove more duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 04:43:11 +00:00
Rafael Espindola
c85dca66e6 Remove duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 04:28:49 +00:00
Evan Cheng
53519f015e Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 18:55:51 +00:00
Bruno Cardoso Lopes
030160073d Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 14:07:40 +00:00
Andrew Trick
c8bfd1d78f Convert -enable-sched-cycles and -enable-sched-hazard to -disable 
flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 05:51:33 +00:00
Evan Cheng
d7e3cc840b Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative 
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 23:55:07 +00:00
Bruno Cardoso Lopes
e47f3751d7 Fix the encoding and parsing of clrex instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
6456121d5c Change instruction names for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123930 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes
8dd37f7b7d Add cdp/cdp2 instructions for thumb/thumb2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
b32f7a5f4b - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
6b3a999f22 Add mcr*2 and mr*c2 support to thumb2 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
fa5bd27fbe Add mcr* and mr*c support to thumb targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes
8197754be5 Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 13:17:59 +00:00
Evan Cheng
907276dc44 Correct itinerary entry for t2MOV_pic_ga_add_pc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123907 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 08:43:03 +00:00
Evan Cheng
9fe2009956 Sorry, several patches in one. 
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 08:34:58 +00:00
Bruno Cardoso Lopes
3abd75bf1d Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 16:56:52 +00:00
Daniel Dunbar
ec91d52a77 ARM/ISel: Factor out isScaledConstantInRange() helper. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 15:12:16 +00:00
Andrew Trick
32cec0a756 For ARM subtargets with useNEONForSinglePrecisionFP, double count uses 
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 02:35:27 +00:00
Andrew Trick
7fa75ce11d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 02:26:13 +00:00
Evan Cheng
fc8475bde9 Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123809 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 02:16:49 +00:00
Bruno Cardoso Lopes
61505907f5 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
e7255a80e3 Fix MRS encoding for arm and thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
892fc6d7b6 Fix the encoding of t2ISB by using the right class and also parse it correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
fdcee77887 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
a461d42228 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:45:56 +00:00
Jim Grosbach
ff12a8bd99 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123769 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 19:59:19 +00:00
Daniel Dunbar
4b462672d2 McARM: Use accessors where appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:55:27 +00:00
Daniel Dunbar
6ec56204f3 McARM: Fill in ASMOperand::dump() for memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:55:21 +00:00
Daniel Dunbar
2637dc9a25 McARM: Make ARMOperand use a union where appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:55:15 +00:00
Daniel Dunbar
05d8b71424 McARM: Unify ParseMemory() successfull return. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123740 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:24 +00:00
Daniel Dunbar
0571093f4c McARM: Early exit on failure (NEFC). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:17 +00:00
Daniel Dunbar
d3df5f32c0 McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic. 
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:11 +00:00
Daniel Dunbar
023835d51b McARM: Add a variety of asserts on the sanity of memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123737 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:34:05 +00:00
Daniel Dunbar
81f453c4b9 McARM: Use a consistent marker for not-set OffsetRegNum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 05:33:57 +00:00
Daniel Dunbar
2e3cea3153 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 03:06:03 +00:00
Jeffrey Yasskin
955ed73d12 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 00:51:23 +00:00