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5391 Commits

Author SHA1 Message Date
Eli Friedman
5e05deebb9 Add -mattr=+sse2 to make the buildbots happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 08:26:26 +00:00
Chad Rosier
86431e9a31 Adding a test case for revision 132825. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 02:44:19 +00:00
Eli Friedman
88b2af7e61 Add a simple test which makes sure folding immediate float zero to a memory operand works. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132824 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 00:30:08 +00:00
Cameron Zwarich
a2e979565b A CCState was being created without setting whether it is in the Call or Prologue state, 
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 22:30:07 +00:00
Eli Friedman
2a6d9eb10b Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809. 
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132809 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 22:14:44 +00:00
Eric Christopher
6f3661fdcd Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 16:03:19 +00:00
Eric Christopher
622ab4ab50 Recommit r132764 since it didn't cause the windows buildbot failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 15:39:01 +00:00
Eric Christopher
7b3f72ff81 Temporarily revert 132764 to see if it fixes the Windows buildbot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 06:29:54 +00:00
Akira Hatanaka
c53cc48ca9 Initial support for inline asm memory operand constraints. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132768 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 03:31:05 +00:00
Eric Christopher
efe12907dd If the alignment of the byval argument is greater than the alignment 
of the frame then increase the maximum alignment of the frame to
match.

Fixes PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 00:15:19 +00:00
Akira Hatanaka
69b9044c66 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132758 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 21:28:09 +00:00
Cameron Zwarich
aaa5f14d7c Fix an issue where the two-address conversion pass incorrectly rewrites untied 
operands to an early clobber register. This fixes <rdar://problem/9566076>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 23:54:00 +00:00
Rafael Espindola
d846e3fb5a Fix a silly error I introduce in r131951. 
Fixes PR10095.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 23:26:45 +00:00
Stuart Hastings
a0dab9cfdf Tweak this test for ARM-hosted 'bot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132711 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 15:23:11 +00:00
Nadav Rotem
1e471820b8 Move the legalizer tests to the X86 directory because the test uses the x86 
codegen. Thanks Galina.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132706 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 05:23:58 +00:00
Akira Hatanaka
8464fff30b Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: 
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 02:17:21 +00:00
Jakob Stoklund Olesen
b3e705f889 Simplify local live range splitting's safeguard to fix PR10070. 
When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.

This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132697 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 23:55:20 +00:00
Stuart Hastings
f99a4b82a4 Followup to 132458, omit unnecessary stack copy when x87 input is a 
load.  rdar://problem/6373334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 23:15:58 +00:00
Nadav Rotem
fc3623bc50 Add methods to support the integer-promotion of vector types. Methods to 
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 20:55:56 +00:00
Stuart Hastings
9a9f8f3ba9 Test case for PR10085. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 20:03:22 +00:00
Eli Friedman
0b4d96baec PR10077: fix fast-isel of extractvalue of aggregate constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 05:46:34 +00:00
Benjamin Kramer
a2898673ac Harden tests for windows path separators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-05 18:20:05 +00:00
Jakob Stoklund Olesen
8f1282d9cb Fix a test that keeps breaking when allocation orders change. 
Who said FileCheck couldn't handle arbitrarily complex conditions?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-04 23:34:40 +00:00
Nadav Rotem
0b66636879 TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132649 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-04 20:58:08 +00:00
Stuart Hastings
865f09334f Reapply 132424 with fixes. This fixes PR10068. 
rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 23:53:54 +00:00
Jakob Stoklund Olesen
2e3e720d76 Fix some tests that depend on register allocation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 22:45:21 +00:00
Eric Christopher
ec281c8934 Another possible bug. Stopgap until we can autogenerate tables and 
constraint lengths.

Part of rdar://9037836 and rdar://9119939



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 22:09:12 +00:00
Eric Christopher
ce1ecf59c8 Fix an off by one error. 
Part of rdar://9037836 and rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 20:44:52 +00:00
Jakob Stoklund Olesen
5f2316a3b5 Switch AllocationOrder to using RegisterClassInfo instead of a BitVector 
of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 20:34:53 +00:00
Eric Christopher
cf714d44b8 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 17:24:37 +00:00
Roman Divacky
0c9b559bfd Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant. 
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 15:47:49 +00:00
Eli Friedman
d6412c940e Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 01:13:19 +00:00
Devang Patel
cf4cc84738 During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. 
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 20:07:12 +00:00
Rafael Espindola
580cbd9cf0 Add test for PR10068. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132482 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 20:02:48 +00:00
Rafael Espindola
251b4a0405 Revert 132424 to fix PR10068. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:57:47 +00:00
Stuart Hastings
552c0ee4f9 Andy pointed out a dumb omission in this test case. Thanks Andy! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:26:49 +00:00
Stuart Hastings
1f344f052e Jakob pointed out a dumb omission in this test case. Thanks Jakob! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 18:44:05 +00:00
Stuart Hastings
84be958ed8 Omit unnecessary stack copy when x87 input is a load. 
rdar://problem/6373334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 15:57:11 +00:00
Stuart Hastings
ac92565384 Tweak testcase for ARM bot. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:05:39 +00:00
Akira Hatanaka
5e06903e66 Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 01:03:14 +00:00
Akira Hatanaka
f876bf81df Test case for r132444. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132445 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 00:25:53 +00:00
Devang Patel
c432907eca Do not drop constant values when a variable's content is described using .debug_loc entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 22:03:25 +00:00
Stuart Hastings
ec880283b3 Recommit 132404 with fixes. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 21:33:14 +00:00
Eric Christopher
9aaa02a1d2 Allow bitcasts between valid types of the same size and vector 
types if the vector type is legal.

Fixes rdar://9306086


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:55:10 +00:00
Stuart Hastings
4abc5fea9c Revert 132404 to appease a buildbot. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:52:20 +00:00
Stuart Hastings
0f971b1fdb Cleanup test case. rdar://problem/5660695 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132408 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 18:23:14 +00:00
Stuart Hastings
10ff0bbdfb Add support for x86 CMPEQSS and friends. These instructions do a 
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 17:17:45 +00:00
Stuart Hastings
d7de954644 A forthcoming SSE patch will break this test; since the test is also 
valid for x87, re-target to x87.  rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 16:13:09 +00:00
Stuart Hastings
b909d35de4 Test case for 132396. rdar://problem/5660695 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 15:50:29 +00:00
Nadav Rotem
b6fbec3a54 This patch is another step in the direction of adding vector select. In this 
patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization.  This flag will be removed when the transition is
complete.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 12:51:46 +00:00