Commit Graph

103447 Commits

Author SHA1 Message Date
Matt Arsenault
ad4e6970a1 Fix using wrong result type for setcc.
When reducing the bitwidth of a comparison against a constant, the
original setcc's result type was used, which was incorrect.

No test since I don't think any other in tree targets change the
bitwidth of the setcc type depending on the bitwidth of the compared
type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208236 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 18:26:58 +00:00
Eric Christopher
bbad52193e Debug.h already includes raw_ostream.h, no need to include it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208235 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 18:19:04 +00:00
Adam Nemet
a822fab74d [Test] Remove c-index-test from the list of substitutions
All the tests are under the clang tests and none should be under llvm moving
forward.

The topic was discussed in this thread:

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 18:16:02 +00:00
Sebastian Pop
5026b2cc8b split delinearization pass in 3 steps
To compute the dimensions of the array in a unique way, we split the
delinearization analysis in three steps:

- find parametric terms in all memory access functions
- compute the array dimensions from the set of terms
- compute the delinearized access functions for each dimension

The first step is executed on all the memory access functions such that we
gather all the patterns in which an array is accessed. The second step reduces
all this information in a unique description of the sizes of the array. The
third step is delinearizing each memory access function following the common
description of the shape of the array computed in step 2.

This rewrite of the delinearization pass also solves a problem we had with the
previous implementation: because the previous algorithm was by induction on the
structure of the SCEV, it would not correctly recognize the shape of the array
when the memory access was not following the nesting of the loops: for example,
see polly/test/ScopInfo/multidim_only_ivs_3d_reverse.ll

; void foo(long n, long m, long o, double A[n][m][o]) {
;
;   for (long i = 0; i < n; i++)
;     for (long j = 0; j < m; j++)
;       for (long k = 0; k < o; k++)
;         A[i][k][j] = 1.0;

Starting with this patch we no longer delinearize access functions that do not
contain parameters, for example in test/Analysis/DependenceAnalysis/GCD.ll

;;  for (long int i = 0; i < 100; i++)
;;    for (long int j = 0; j < 100; j++) {
;;      A[2*i - 4*j] = i;
;;      *B++ = A[6*i + 8*j];

these accesses will not be delinearized as the upper bound of the loops are
constants, and their access functions do not contain SCEVUnknown parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208232 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 18:01:20 +00:00
Chandler Carruth
905e33545c [x86] Make the 'x86-64' cpu, what I see as and many use as the generic
default architecture for reasonable modern x86 processors, actually be
modern. This processor model should essentially be "tuned" for modern
x86 chips as much as possible without undue penalties on any specific
architecture. Previously we weren't even using the nice scheduling
models. There are a few other tweaks needed here, but this change at
least I have benchmarked across a decent swatch of chips (intel's
clovertown, westmere, and sandybridge; amd's istanbul) and seen no
significant regressions.

If anyone has suggested ways to test this, just let me know. Somewhat
alarmingly, no existing tests failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208230 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 17:37:03 +00:00
Chandler Carruth
40b514dc28 Tidy up whitespace with clang-format prior to making significant
changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 17:36:59 +00:00
Simon Atanasyan
d92c843b2e [yaml2obj] Support ELF x86 relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208228 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 17:06:38 +00:00
Rafael Espindola
4d88db0d81 Style update: don't duplicate the function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208227 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 17:04:45 +00:00
Alexey Samsonov
0f0974ddb9 [CMake] Add build rules for llvm-PerfectShuffle utility
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208225 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:54:00 +00:00
Rafael Espindola
3a163b7692 Style update: don't duplicate the function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208224 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:43:23 +00:00
Chad Rosier
8f0f458824 [ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,
this patch disables the dead register elimination pass and the load/store pair
optimization pass at -O0.  The ILP optimizations don't require the optimization
level to be checked because the call to addILPOpts is predicated with the
necessary check.  The AdvSIMDScalar pass is disabled by default at all
optimization levels.  This patch leaves that pass disabled by default.

Also, move command-line options into ARM64TargetMachine.cpp and add a few
additional flags to aid in debugging.  This fixes an issue with the
-debug-pass=Structure flag where passes were printed, but not actually run
(i.e., AdvSIMDScalar pass).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208223 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:41:55 +00:00
Daniel Sanders
7858e495e9 [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).

The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.

Reviewers: vmedic

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D3569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208221 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:25:22 +00:00
Justin Bogner
459a8aaee2 llvm-cov: Explicitly namespace llvm::make_unique to keep MSVC happy
This is a followup to r208171, where a call to make_unique was
disambiguated for MSVC. Disambiguate two more calls, and remove the
comment about it since this is what we do everywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208219 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:01:27 +00:00
Rafael Espindola
6cf16a40d3 Use range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208218 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:53:32 +00:00
Michael Zolotukhin
355e0a6460 [InstCombine] Add optimization of redundant insertvalue instructions.
rdar://problem/11861387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208214 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:30:18 +00:00
Daniel Sanders
0c78010b88 [mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates
Summary:
No functional change (confirmed by diffing tablegen-erated files).

Depends on D3642

Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208213 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:25:43 +00:00
Daniel Sanders
b49c582218 [mips] Add INSN_<name> adverbs and start using them instead of AdditionalPredicates overrides
Summary:
No functional change

Depends on D3641

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208212 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:11:46 +00:00
Evgeniy Stepanov
8a387a7aee [msan] Fix -fsanitize=memory -fno-integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:10:51 +00:00
Tim Northover
04a359f768 AArch64/ARM64: optimise vector selects & enable test
When performing a scalar comparison that feeds into a vector select,
it's actually better to do the comparison on the vector side: the
scalar route would be "CMP -> CSEL -> DUP", the vector is "CM -> DUP"
since the vector comparisons are all mask based.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208210 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:10:27 +00:00
Daniel Sanders
b1c5f88237 [mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides
Summary:
One small functional change. The recently added PAUSE instruction now has
the HasStdEnc predicate which was accidentally removed by a Requires<>.

Depends on D3640

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 13:57:22 +00:00
Rafael Espindola
2842c051b3 Remove the UseCFI option from createAsmStreamer.
We were already always passing true, this just removes the option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 13:00:43 +00:00
Ed Maste
fe0b2279a8 DebugInfo: Use enum instead of unsigned
This makes debuging DebugInfo generation with LLDB a little more pleasant.

Differential Revision: http://reviews.llvm.org/D3626


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208202 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:49:08 +00:00
Daniel Sanders
b2d170d61b [mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3639

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208201 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:48:37 +00:00
James Molloy
2712c87cfe [ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:55 +00:00
James Molloy
d93d214a67 [ARM64-BE] Fix variable-argument saving.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:48 +00:00
James Molloy
fca7f5c585 [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
The AAPCS states that values passed in registers must have a value as though
they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is,
loading scalars to vector registers and loading 1-element vectors is equivalent.

The logic implemented here is to ensure that at all call boundaries and during
formal argument lowering all vectors are treated as their bitwidth-based floating
point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64,
v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be
generated during code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:41 +00:00
Daniel Sanders
1caec99d5d [mips] Move IsFP64bit/NotFP64bit to the front of the AdditionalPredicates list
Summary:
This makes it easier to prove a more complicated change in the next commit
is non-functional.

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3639

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:27:46 +00:00
James Molloy
737c2ac4fc [ARM64-BE] Implement the crazy bitcast handling for big endian vectors.
Because we've canonicalised on using LD1/ST1, every time we do a bitcast
between vector types we must do an equivalent lane reversal.

Consider a simple memory load followed by a bitconvert then a store.
  v0 = load v2i32
  v1 = BITCAST v2i32 v0 to v4i16
       store v4i16 v2

In big endian mode every memory access has an implicit byte swap. LDR and
STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
is, they treat the vector as a sequence of elements to be byte-swapped.
The two pairs of instructions are fundamentally incompatible. We've decided
to use LD1/ST1 only to simplify compiler implementation.

LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
the original code sequence:  v0 = load v2i32

  v1 = REV v2i32                  (implicit)
  v2 = BITCAST v2i32 v1 to v4i16
  v3 = REV v4i16 v2               (implicit)
       store v4i16 v3

But this is now broken - the value stored is different to the value loaded
due to lane reordering. To fix this, on every BITCAST we must perform two
other REVs:

  v0 = load v2i32
  v1 = REV v2i32                  (implicit)
  v2 = REV v2i32
  v3 = BITCAST v2i32 v2 to v4i16
  v4 = REV v4i16
  v5 = REV v4i16 v4               (implicit)
       store v4i16 v5

This means an extra two instructions, but actually in most cases the two REV
instructions can be combined into one. For example:
  (REV64_2s (REV64_4h X)) === (REV32_4h X)

There is also no 128-bit REV instruction. This must be synthesized with an
EXT instruction.

Most bitconverts require some sort of conversion. The only exceptions are:
  a) Identity conversions -  vNfX <-> vNiX
  b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX

Even though there are hundreds of changed lines, I have a fairly high confidence
that they are somewhat correct. The changes to add two REV instructions per
bitcast were pretty mechanical, and once I'd done that I threw the resulting
.td at a script I wrote which combined the two REVs together (and added
an EXT instruction, for f128) based on an instruction description I gave it.

This was much less prone to error than doing it all manually, plus my brain
would not just have melted but would have vapourised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:53 +00:00
James Molloy
1f890ce2dc [ARM64-BE] Predicate VLDR/VSTR for vectors as little-endian only. We must use LD1/ST1 on big-endian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:45 +00:00
James Molloy
104629cc7c [ARM64-BE] Make big endian (scalar) argument passing work correctly.
This completes the port of r204814 (cpirker "AArch64_BE function argument
passing for ARM ABI") from AArch64 to ARM64, and fixes a bunch of issues
found during later development along the way. The biggest of these was
that the alignment fixup logic wasn't replicated into all the places it
should have been.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:36 +00:00
Stepan Dyatkovskiy
9b363106f3 MergeFunctions Pass, introduced total ordering among values.
This is a third patch of patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

This patch description:
Being comparing functions we need to compare values we meet at left and
right sides.
Its easy to sort things out for external values. It just should be
the same value at left and right.
But for local values (those were introduced inside function body)
we have to ensure they were introduced at exactly the same place,
and plays the same role.

In short, patch introduces values serial numbering and comparison routine.
The last one compares two values by their serial numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208189 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:11:39 +00:00
Tim Northover
0d427515b3 AArch64/ARM64: run test on ARM64 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208188 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:47:04 +00:00
Tim Northover
5a1d5139b8 AArch64/ARM64: put annotation in test
It makes finding already covered tests much easier with "grep -L
arm64".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:47:00 +00:00
Tim Northover
c6f683627d AArch64/ARM64: disable test directory if ARM64 not present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:42:06 +00:00
Daniel Sanders
a3953a30b6 [mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.

This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.

It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3549, D3506

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3550

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208184 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:27:09 +00:00
Daniel Sanders
d80222a48b [tablegen] Add !listconcat operator with the similar semantics as !strconcat
Summary:
It concatenates two or more lists. In addition to the !strconcat semantics
the lists must have the same element type.

My overall aim is to make it easy to append to Instruction.Predicates
rather than override it. This can be done by concatenating lists passed as
arguments, or by concatenating lists passed in additional fields.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D3506

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208183 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:13:19 +00:00
Daniel Sanders
0c9ea21554 [mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.

No functional change.

Depends on D3506

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:58:05 +00:00
Zinovy Nis
6a48f1c271 [BUG][REFACTOR]
1) Fix for printing debug locations for absolute paths.
2) Location printing is moved into public method DebugLoc::print() to avoid re-inventing the wheel.

Differential Revision: http://reviews.llvm.org/D3513




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208177 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:51:22 +00:00
Stepan Dyatkovskiy
cb3a147870 Second patch of patch series that improves MergeFunctions performance time from O(N*N) to
O(N*log(N)). The idea is to introduce total ordering among functions set.
It allows to build binary tree and perform function look-up procedure in O(log(N)) time. 

This patch description:
Introduced total ordering among constants implemented in cmpConstants method.
Method performs lexicographical comparison between constants represented as
hypothetical numbers of next format:
<bitcastability-trait><raw-bit-contents>

Please, read cmpConstants declaration comments for more details.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 09:05:10 +00:00
Timur Iskhodzhanov
88ab50c237 Work-around MSVS build breakage due to r208148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 08:52:13 +00:00
Evgeniy Stepanov
227c4c6185 [asan] Add a flag to control asm instrumentation.
With this change, asm instrumentation is disabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208167 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 07:54:11 +00:00
Joerg Sonnenberger
2ecdcdc026 Allow using normal .eh_frame based unwinding on ARM. Use the same
encodings as x86. Use this exception model for NetBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208166 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 07:49:34 +00:00
David Blaikie
8a25ee1440 PR19562: DebugInfo temporary MDNode leak: Don't include a temporary node to replace with a variable list for methods, since they're always declarations and thus never include variables
This field is used for a list of variables to ensure they are not lost
during optimization (they're only included when optimizations are
enabled).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208159 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 06:08:28 +00:00
Tobias Grosser
a1f8bd6753 [C++11] Add NArySCEV->Operands iterator range
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208158 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 06:07:47 +00:00
Simon Atanasyan
111454f4e9 [obj2yaml] Recognize input file format using llvm::object::ObjectFile
interface methods isCOFF().

The '-coff' command line option has been removed. It was not used in any
test cases.

The patch reviewed by Michael Spencer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208157 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 05:18:51 +00:00
Saleem Abdulrasool
3fe09b705c ARM: mark additional instructions as MachineFrameSetup
Mark up additional instructions which are part of the function prologue as
MachineFrameSetup.  These instructions are part of the function prologue,
emitted by the PEI pass to setup the stack for use in the activating frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208153 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 03:03:31 +00:00
Saleem Abdulrasool
0029e2d665 ARM: fix WoA PEI instruction selection
The ARM::BLX instruction is an ARM mode instruction.  The Windows on ARM target
is limited to Thumb instructions.  Correctly use the thumb mode tBLXr
instruction.  This would manifest as an errant write into the object file as the
instruction is 4-bytes in length rather than 2.  The result would be a corrupted
object file that would eventually result in an executable that would crash at
runtime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208152 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 03:03:27 +00:00
Justin Bogner
ffb8718ee5 llvm-cov: Document --no-output in the command guide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208151 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:33:58 +00:00
Justin Bogner
c92330c18c llvm-cov: Handle missing source files as GCOV does
If the source files referenced by a gcno file are missing, gcov
outputs a coverage file where every line is simply /*EOF*/.  This also
occurs for lines in the coverage that are past the end of a file that
is found.

This change mimics gcov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208149 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:11:23 +00:00
Justin Bogner
56d05e468c llvm-cov: Implement --no-output
In gcov, there's a -n/--no-output option, which disables the writing
of any .gcov files, so that it emits only the summary info on stdout.
This implements the same behaviour in llvm-cov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:11:18 +00:00