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Author SHA1 Message Date
Chris Lattner
c3c021bcad Fix a problem where were were literally selecting for INCREASED register 
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19697 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 17:24:34 +00:00
Chris Lattner
2a6e163edc Just in case, handle something that is both a use and a def. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19696 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 17:11:51 +00:00
Chris Lattner
d45be36965 When an instruction moves, make sure to update the VarInfo::Kills list as 
well as all of teh other stuff in livevar. This fixes the compiler crash
on fourinarow last night.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19695 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 17:09:15 +00:00
Chris Lattner
a76f04828a When commuting these instructions, make sure to actually swap the operands too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19694 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 16:55:52 +00:00
Chris Lattner
7d719c3cd8 Fix 'raise' to work with packed types. Patch by Morten Ofstad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19693 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 16:16:35 +00:00
Chris Lattner
4053b1e30b Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (which 
typically cost 1 cycle) instead of shld/shrd instruction (which are typically
6 or more cycles).  This also saves code space.

For example, instead of emitting:

rotr:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %CL, BYTE PTR [%ESP + 8]
        shrd %EAX, %EAX, %CL
        ret
rotli:
        mov %EAX, DWORD PTR [%ESP + 4]
        shrd %EAX, %EAX, 27
        ret

Emit:

rotr32:
        mov %CL, BYTE PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, %CL
        ret
rotli32:
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, 27
        ret

We also emit byte rotate instructions which do not have a sh[lr]d counterpart
at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19692 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 08:07:05 +00:00
Chris Lattner
b51f2e3de2 New testcase for rotate instructions. Each function should codegen to a 
rotate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19691 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 08:04:08 +00:00
Chris Lattner
40ff633b05 Add rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19690 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 07:50:03 +00:00
Chris Lattner
30ea1e9411 Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19689 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 07:37:26 +00:00
Chris Lattner
39d6396d01 Add a test for 16-bit sh*d. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19688 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 07:37:01 +00:00
Chris Lattner
0df53d22c3 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19687 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 07:31:24 +00:00
Chris Lattner
41e431ba04 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 07:11:01 +00:00
Chris Lattner
c71d6949b9 Use the TargetInstrInfo::commuteInstruction method to commute instructions 
instead of doing it manually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19685 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 07:08:42 +00:00
Chris Lattner
167b10cba4 Finegrainify namespacification 
Add default impl of commuteInstruction
Add notes about ugly V9 code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19684 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 06:53:34 +00:00
Chris Lattner
d7e2fe40e4 Add a new method, described in the comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19683 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 06:53:02 +00:00
Chris Lattner
7c79de7c65 Ensure that each these functions generates a sh[rl]d instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19682 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 06:30:36 +00:00
Chris Lattner
8571637ee9 Codegen long >> 2 to this: 
foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shrd %EAX, %EDX, 2
        sar %EDX, 2
        ret

instead of this:

test1:
        mov %ECX, DWORD PTR [%ESP + 4]
        shr %ECX, 2
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %EDX
        shl %EAX, 30
        or %EAX, %ECX
        sar %EDX, 2
        ret

and long << 2 to this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
***     mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        shr %ECX, 30
        mov %EDX, DWORD PTR [%ESP + 8]
        shl %EDX, 2
        or %EDX, %ECX
        shl %EAX, 2
        ret

The extra copy (marked ***) can be eliminated when I teach the code generator
that shrd32rri8 is really commutative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19681 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 06:18:43 +00:00
Jeff Cohen
8e1971bda2 Add missing data types for VC++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19680 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 05:08:31 +00:00
Chris Lattner
e34b396ab7 Implement a way of expanding shifts. This applies to targets that offer 
select operations or to shifts that are by a constant.  This automatically
implements (with no special code) all of the special cases for shift by 32,
shift by < 32 and shift by > 32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19679 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 04:19:40 +00:00
Chris Lattner
009b55b6f6 X86 shifts mask the amount. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19678 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 03:36:30 +00:00
Chris Lattner
d6e496732b Add a hook to find out how the target handles shift amounts that are out of 
range.  Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).

This defaults to undefined, which is conservatively correct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19677 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 03:36:14 +00:00
Chris Lattner
6147a7aa17 Move all data members to the end of the class. 
Add a hook to find out how the target handles shift amounts that are out of
range.  Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).

This defaults to undefined, which is conservatively correct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19676 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-19 03:36:03 +00:00
Chris Lattner
d5d5682512 Zero is cheaper than sign extend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19675 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 21:57:59 +00:00
Chris Lattner
477c931852 Code to handle FP_EXTEND is dead now. X86 doesn't support any data types to 
FP_EXTEND from!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19674 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 20:05:56 +00:00
Chris Lattner
3dd68151dc Remove more dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19673 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 19:50:08 +00:00
Chris Lattner
a7a4c0f7c4 The selection dag code handles the promotions from F32 to F64 for us, so we 
don't need to even think about F32 in the X86 code anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19672 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 19:46:54 +00:00
Chris Lattner
47e9223e06 Fix some fixmes (promoting bools for select and brcond), fix promotion 
of zero and sign extends.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19671 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 19:27:06 +00:00
Chris Lattner
4a9b4f1943 Keep track of the retval type as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19670 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 19:26:36 +00:00
Chris Lattner
c7ba0eb5eb Keep track of the returned value type as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19669 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 19:26:18 +00:00
Chris Lattner
ef5cd1d3cf Teach legalize to promote copy(from|to)reg, instead of making the isel pass 
do it.  This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19668 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 17:54:55 +00:00
Chris Lattner
b422aeac9e Fix 124.m88ksim. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19667 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 17:35:28 +00:00
Jeff Cohen
abce77b710 Add project llvm-ld to Visual Studio 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19665 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 05:44:50 +00:00
Jeff Cohen
a877e1baa9 Add project llvm-nm to Visual Studio 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19664 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 05:44:25 +00:00
Jeff Cohen
3faf059132 Add project llvm-ld to Visual Studio 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19663 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 05:39:37 +00:00
Jeff Cohen
728324e848 Add llvm-bcanalyzer project to Visual Studio 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19662 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 05:31:34 +00:00
Chris Lattner
811482a82b Do not emit loads multiple times, potentially in the wrong places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19661 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 04:18:32 +00:00
Tanya Lattner
0111474bde Minor changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19660 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 04:15:41 +00:00
Chris Lattner
b71f8fc99d Eliminate bad assertions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19659 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 04:00:54 +00:00
Chris Lattner
4a108668df * Eliminate the TokenSet and just use the ExprMap for both tokens and values. 
* Insert some really pedantic assertions that will notice when we emit the
  same loads more than one time, exposing bugs.  This turns a miscompilation in
  bzip2 into a compile-fail.  yaay.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19658 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 03:51:59 +00:00
Chris Lattner
82fbfb6984 Teach legalize to promote SetCC results. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19657 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 02:59:52 +00:00
Chris Lattner
f30b73b1c6 Allow setcc operations to have nonbool types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19656 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 02:52:03 +00:00
Chris Lattner
30c0fc23c5 Allow setcc operations to have non-bool types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19655 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 02:51:41 +00:00
Chris Lattner
883c86f510 Rely on the code in MatchAddress to do this work. Otherwise we fail to 
match (X+Y)+(Z << 1), because we match the X+Y first, consuming the index
register, then there is no place to put the Z.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19652 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 02:25:52 +00:00
Chris Lattner
6e4e7652d8 Fix the completely broken FP constant folds for setcc's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19651 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 02:11:55 +00:00
Chris Lattner
98a8ba0393 Fix a problem where probing for addressing modes caused expressions to be 
emitted too early.  In particular, this fixes
Regression/CodeGen/X86/regpressure.ll:regpressure3.

This also improves the 2nd basic block in 164.gzip:flush_block, which went from

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree + 20]
        movzx %ECX, WORD PTR [dyn_ltree + 16]
        mov DWORD PTR [%ESP + 32], %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        movzx %EDX, WORD PTR [dyn_ltree + 8]
        movzx %EBX, WORD PTR [dyn_ltree + 4]
        mov DWORD PTR [%ESP + 36], %EBX
        movzx %EBX, WORD PTR [dyn_ltree]
        add DWORD PTR [%ESP + 36], %EBX
        add %EDX, DWORD PTR [%ESP + 36]
        add %ECX, %EDX
        add DWORD PTR [%ESP + 32], %ECX
        add %EAX, DWORD PTR [%ESP + 32]
        movzx %ECX, WORD PTR [dyn_ltree + 24]
        add %EAX, %ECX
        mov %ECX, 0
        mov %EDX, %ECX

to

.LBBflush_block_1:      # loopentry.1.i
        movzx %EAX, WORD PTR [dyn_ltree]
        movzx %ECX, WORD PTR [dyn_ltree + 4]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 8]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 12]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 16]
        add %EAX, %ECX
        movzx %ECX, WORD PTR [dyn_ltree + 20]
        add %ECX, %EAX
        movzx %EAX, WORD PTR [dyn_ltree + 24]
        add %ECX, %EAX
        mov %EAX, 0
        mov %EDX, %EAX

... which results in less spilling in the function.

This change alone speeds up 164.gzip from 37.23s to 36.24s on apoc.  The
default isel takes 37.31s.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19650 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-18 01:06:26 +00:00
Chris Lattner
e9fe2bcac2 Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19649 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-17 23:25:45 +00:00
Chris Lattner
a8b6f68a55 This is a carefully contrived testcase where the X86 ISel is emitting all loads 
before other ops, causing it to spill like mad.  This occurs in
164.gzip:flush_block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19648 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-17 23:16:01 +00:00
Chris Lattner
869e0434ae Don't bother using max here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19647 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-17 23:02:13 +00:00
Chris Lattner
90d1be7eef Do not give token factor nodes outrageous weights 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19645 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-17 22:56:09 +00:00
Chris Lattner
d3948116b8 Non-volatile loads can be freely reordered against each other. This fixes 
X86/reg-pressure.ll again, and allows us to do nice things in other cases.
For example, we now codegen this sort of thing:

int %loadload(int *%X, int* %Y) {
  %Z = load int* %Y
  %Y = load int* %X      ;; load between %Z and store
  %Q = add int %Z, 1
  store int %Q, int* %Y
  ret int %Y
}

Into this:

loadload:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%EAX]
        mov %ECX, DWORD PTR [%ESP + 8]
        inc DWORD PTR [%ECX]
        ret

where we weren't able to form the 'inc [mem]' before.  This also lets the
instruction selector emit loads in any order it wants to, which can be good
for register pressure as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19644 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-17 22:19:26 +00:00