Commit Graph

2821 Commits

Author SHA1 Message Date
Matheus Almeida
f7b6bac262 [mips][msa] Direct Object Emission support for the LSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 13:20:07 +00:00
Artyom Skrobov
b161955ffb Make ARM hint ranges consistent, and add tests for these ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 10:14:40 +00:00
David Blaikie
2b3ea3cdad MC: Support multiple sections with the same name in the same comdat group
Code review by Eric Christopher and Rafael Espindola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-22 23:41:52 +00:00
Tim Northover
01b0e94bb7 ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-22 19:00:39 +00:00
Matheus Almeida
5cb5ff8b14 [mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-22 09:43:32 +00:00
Matheus Almeida
348da8d6b5 [mips][msa] Direct Object Emission support for LD/ST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 13:07:13 +00:00
Matheus Almeida
b14ad46549 [mips][msa] Direct Object Emission support for LDI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193081 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:56:20 +00:00
Matheus Almeida
f6d4cff9b1 [mips][msa] Direct Object Emission support for MOVE.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:43:54 +00:00
Matheus Almeida
006cff8d7b [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:26:50 +00:00
Matheus Almeida
cebd401022 [mips][msa] Direct Object Emission of SPLAT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:07:26 +00:00
Matheus Almeida
f89f66e61b [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 11:47:56 +00:00
Peter Collingbourne
e52fac1632 Emit DWARF line entries for all data in the instruction stream.
r182712 attempted to do this, but it failed to handle data emitted via
EmitBytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-20 02:16:18 +00:00
Hans Wennborg
22f9dd4591 MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asm
This is another (final?) stab at making us able to parse our own asm output
on Windows.

Symbols on Windows often contain @'s and ?'s in their names. Our asm parser
didn't like this. ?'s were not allowed, and @'s were intepreted as trying to
reference PLT/GOT/etc.

We can't just add quotes around the bad names, since e.g. for MinGW, we use gas
to assemble, and it doesn't like quotes in some places (notably in .def
directives).

This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS
assembly.

Differential Revision: http://llvm-reviews.chandlerc.com/D1978

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193000 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 20:46:28 +00:00
Richard Barton
485333df71 Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 14:09:49 +00:00
Chad Rosier
c439c205ba [AArch64] Add support for NEON scalar extract narrow instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 14:03:24 +00:00
Silviu Baranga
b1c480900b Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 10:18:40 +00:00
Hans Wennborg
ab887bf52c Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"
This caused the clang-native-mingw32-win7 buildbot to break.

The assembler was complaining about the following lines that were showing up
in the asm for CrashRecoveryContext.cpp:

  movl  $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax)
  calll "_AddVectoredExceptionHandler@8"
  .def   "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4";
  "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4":
  calll "_RemoveVectoredExceptionHandler@4"

Reverting for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 02:14:40 +00:00
Chad Rosier
3b370a2ac4 [AArch64] Add support for NEON scalar three register different instruction
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 18:12:29 +00:00
Hans Wennborg
b74b88edac Re-commit r192758 - MC: quote tricky symbol names in asm output
The reason this got reverted was that the @feat.00 symbol which was emitted
for every TU became quoted, and on cygwin/mingw we use the gas assembler which
couldn't handle the quotes.

This commit fixes the problem by only emitting @feat.00 for win32, where we use
clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no
loss there.

With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since
it uses the Itanium ABI, which doesn't put these funny characters in symbols.

> Because of win32 mangling, we produce symbol and section names with
> funny characters in them, most notably @ characters.
>
> MC would choke on trying to parse its own assembly output. This patch addresses
> that by:
>
> - Making @ trigger quoting of symbol names
> - Also quote section names in the same way
> - Just parse section names like other identifiers (to allow for quotes)
> - Don't assume @ signifies a symbol variant if it is in a string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192859 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 01:13:02 +00:00
Chad Rosier
dceac4c5a6 [AArch64] Add support for NEON scalar negate instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 21:04:39 +00:00
Chad Rosier
a249914462 [AArch64] Add support for NEON scalar absolute value instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 21:04:34 +00:00
Chad Rosier
8225b23c6a Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 16:30:10 +00:00
Chad Rosier
a2cd42a0a7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 16:09:02 +00:00
NAKAMURA Takumi
32c24da373 Revert r192758 (and r192759), "MC: Better handling of tricky symbol and section names"
GNU AS didn't like quotes in symbol names.

    Error: junk at end of line, first unrecognized character is `"'

        .def "@feat.00";
        "@feat.00" = 1

Reproduced on Cygwin's 2.23.52.20130309 and mingw32's 2.20.1.20100303.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 08:22:49 +00:00
Hans Wennborg
d910c46963 dos2unix on quoted-names.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 01:22:07 +00:00
Hans Wennborg
508d7b7330 MC: Better handling of tricky symbol and section names
Because of win32 mangling, we produce symbol and section names with
funny characters in them, most notably @ characters.

MC would choke on trying to parse its own assembly output. This patch addresses
that by:

- Making @ trigger quoting of symbol names
- Also quote section names in the same way
- Just parse section names like other identifiers (to allow for quotes)
- Don't assume @ signifies a symbol variant if it is in a string.

Differential Revision: http://llvm-reviews.chandlerc.com/D1945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16 01:20:40 +00:00
Chad Rosier
1824bd0ef8 [AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 21:18:44 +00:00
Akira Hatanaka
b004913417 [mips] Set HI/LO registers' HWEncoding field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192661 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 01:00:00 +00:00
Chad Rosier
942827b113 [AArch64] Add support for NEON scalar integer compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 14:37:20 +00:00
Bernard Ogden
7220572e74 Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 13:16:57 +00:00
Matheus Almeida
9672a89c71 [mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 13:07:39 +00:00
Matheus Almeida
e89c50acc8 [mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 12:57:18 +00:00
Matheus Almeida
01436ba306 [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 12:38:17 +00:00
Matheus Almeida
29adbe8464 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 12:22:43 +00:00
Matheus Almeida
45ecbfc8e5 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 11:49:30 +00:00
Craig Topper
c6f7c99809 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 04:55:01 +00:00
Craig Topper
8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 01:42:32 +00:00
Craig Topper
bae9f69d37 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 01:21:22 +00:00
Benjamin Kramer
5af763cb2a Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 19:05:08 +00:00
Amara Emerson
fc3dc102e0 [ARM] Fix FP ABI attributes with no VFP enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 16:03:43 +00:00
Matheus Almeida
21d60f02c3 This reverts 192447 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:58:32 +00:00
Matheus Almeida
abba71663e This reverts r192449 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:56:12 +00:00
Matheus Almeida
62a69eee5a [mips][msa] Direct Object Emission for the majority of the ELM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:39:49 +00:00
Matheus Almeida
6f36ea5c47 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:29:36 +00:00
Kevin Qin
767f816b92 Implement aarch64 neon instruction set AdvSIMD (copy).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 02:33:55 +00:00
Hao Liu
6a5a667517 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 17:00:52 +00:00
Rafael Espindola
812ddcc50f Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 15:15:17 +00:00
Hao Liu
d622bef31d Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 15:01:24 +00:00
Craig Topper
15de63cfde Allow non-AVX form of pmovmskb to take a GR64 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 05:33:31 +00:00
Tim Northover
ccb06ae8f3 AArch64: migrate ADRP relaxation test to be llvm-mc only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-09 07:53:49 +00:00