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87 Commits

Author SHA1 Message Date
Ana Pazos
a53bf06f7a Implemented aarch64 Neon scalar vmulx_lane intrinsics 
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 23:32:10 +00:00
Chad Rosier
5758c3c832 [AArch64] Fix the scalar NEON ACLE functions so that they return float/double 
rather than the vector equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 21:28:10 +00:00
Kevin Qin
27df434c5e Add test case for AArch64 NEON instruction set misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 06:45:17 +00:00
Kevin Qin
a08063a000 Implement aarch64 neon instruction class SIMD misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 02:44:13 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 01:57:32 +00:00
Chad Rosier
11966d7c98 [AArch64] Add support for legacy AArch32 NEON scalar shift by immediate 
instructions.  This patch does not include the shift right and accumulate
instructions.  A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194598 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 20:05:37 +00:00
Chad Rosier
4c433cf673 [AArch64] The shift right/left and insert immediate builtins expect 3 
source operands, a vector, an element to insert, and a shift amount.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194406 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 19:11:11 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 18:04:07 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 02:25:49 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 17:42:05 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 03:39:32 +00:00
Kevin Qin
8263dcdf23 Implemented aarch64 neon intrinsic vcopy_lane with float type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 02:03:59 +00:00
Tim Northover
627ef0cf5e AArch64: use default asm operand printing when modifier inapplicable 
If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.

Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194024 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-04 23:04:07 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 22:36:59 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 19:28:44 +00:00
Amara Emerson
c2884320fe [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 09:32:11 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 15:19:37 +00:00
Weiming Zhao
a72ec5517f add test cases for frameaddr and returnaddr for aarch64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 17:01:29 +00:00
Tim Northover
fd4937fe2a AArch64: add 'a' inline asm operand modifier 
This is used in the Linux kernel, and effectively just means "print an
address".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193593 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 08:22:33 +00:00
Rafael Espindola
9540074467 Convert another llc -filetype=obj test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193538 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 21:06:12 +00:00
Rafael Espindola
ade09c7fe7 Convert another llc -filetype=obj test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 20:59:41 +00:00
Rafael Espindola
e2f60cf7f1 Convert another llc -filetype=obj test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193536 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 20:54:33 +00:00
Rafael Espindola
164bd156fc Convert a llc -filetype=obj test into a llvm-mc test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193534 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 20:40:20 +00:00
Amara Emerson
2f21452ba1 [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. 
When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-24 08:28:24 +00:00
Chad Rosier
b5eae81267 [AArch64] Add the constraint to NEON scalar mla/mls instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193117 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-21 20:11:47 +00:00
Chad Rosier
c439c205ba [AArch64] Add support for NEON scalar extract narrow instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-18 14:03:24 +00:00
Chad Rosier
3b370a2ac4 [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-17 18:12:29 +00:00
Chad Rosier
dceac4c5a6 [AArch64] Add support for NEON scalar negate instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 21:04:39 +00:00
Chad Rosier
a249914462 [AArch64] Add support for NEON scalar absolute value instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 21:04:34 +00:00
Chad Rosier
a2cd42a0a7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 16:09:02 +00:00
Chad Rosier
1824bd0ef8 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-15 21:18:44 +00:00
Chad Rosier
942827b113 [AArch64] Add support for NEON scalar integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 14:37:20 +00:00
Kevin Qin
767f816b92 Implement aarch64 neon instruction set AdvSIMD (copy). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 02:33:55 +00:00
Hao Liu
6a5a667517 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:00:52 +00:00
Rafael Espindola
812ddcc50f Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." 
This reverts commit r192352. It broke the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 15:15:17 +00:00
Hao Liu
d622bef31d Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 15:01:24 +00:00
Tim Northover
d29bae8bc9 AArch64: enable MISched by default. 
Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.

There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 07:53:57 +00:00
Tim Northover
ccb06ae8f3 AArch64: migrate ADRP relaxation test to be llvm-mc only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192281 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 07:53:49 +00:00
Chad Rosier
c976500793 [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 22:09:04 +00:00
Chad Rosier
3dfe644f7b [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point 
convert instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 20:43:30 +00:00
Chad Rosier
2aeb4771a6 [AArch64] Add support for NEON scalar arithmetic instructions: 
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 16:36:15 +00:00
Jiangning Liu
beb6afa843 Implement aarch64 neon instruction set AdvSIMD (Across). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 08:22:10 +00:00
Jiangning Liu
dd518bcc9d Implement aarch64 neon instruction set AdvSIMD (3V elem). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 09:20:44 +00:00
NAKAMURA Takumi
b2d2575bd8 llvm/test/CodeGen/AArch64/neon-scalar-reduce-pairwise.ll: Use -mtriple here, or aach64-pecoff might be misassumed on win32 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191275 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 04:14:29 +00:00
Jiangning Liu
477fc628b3 Initial support for Neon scalar instructions. 
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 02:47:27 +00:00
Kevin Qin
e54360be01 Implement 3 AArch64 neon instructions : umov smov ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-17 02:21:02 +00:00
Jiangning Liu
959cd8f49b Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions, 
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-09 02:20:27 +00:00
Hao Liu
19fdc268c3 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions: 
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 09:28:24 +00:00
Hao Liu
52d35c2460 A minor change for an obvous problem caused by r188451: 
def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 63;}]>{
As it seems Imm <63 should be Imm <= 63. ImmLeaf is used in pattern match, but there is already a function check the shift amount range, so just remove ImmLeaf. Also add a test to check 63.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188911 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-21 17:47:53 +00:00