Jim Grosbach
c3635c2e92
ARM parsing and encoding tests for MVN
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:37:08 +00:00
Jim Grosbach
ab40f4b737
ARM assembly parsing of MUL instruction.
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Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:20:31 +00:00
Jim Grosbach
b29b4dd988
Tweak ARM assembly parsing and printing of MSR instruction.
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The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 22:45:10 +00:00
Jim Grosbach
80d01dd3d1
ARM assembly parsing of MRS instruction.
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Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 21:59:29 +00:00
Jim Grosbach
ccfd9313d1
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
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Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:35:35 +00:00
Jim Grosbach
2317fe1584
Move mr[r]c[2] ARM tests and tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:28:56 +00:00
Jim Grosbach
1a2be4db5b
ARM testcases for MOVT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:23:25 +00:00
Jim Grosbach
5f16057d1e
ARM assembly parsing for MOV (register).
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Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:10:31 +00:00
Jim Grosbach
ffa3225e26
ARM assembly parsing for MOV (immediate).
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Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 19:13:28 +00:00
Jim Grosbach
0ec2aa21d0
Whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 19:02:39 +00:00
Eli Friedman
7105259ce8
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 02:41:28 +00:00
Eli Friedman
5232cc675c
PR10370: Make sure we know how to relax push correctly on x86-64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 21:28:39 +00:00
Owen Anderson
43967a97cf
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 18:46:47 +00:00
Jim Grosbach
33c16a2737
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
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For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 22:04:21 +00:00
Jim Grosbach
70d8fcfaa0
Add some testcases for ARM MLA/MLS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:43:05 +00:00
Jim Grosbach
c8ae39e746
ARM MCRR/MCRR2 immediate operand range checking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c
ARM MCR/MCR2 assembly parsing operand constraints.
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The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:19:17 +00:00
Jim Grosbach
1134be2428
Enable some tests we now handle correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:02:23 +00:00
Jim Grosbach
3b14a5c546
Update ARM Assembly of LDM/STM.
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ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:35:38 +00:00
Jim Grosbach
791feea100
ARM ISB assembly parsing tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:02:25 +00:00
Jim Grosbach
9dec507ecb
ARM ISB instruction assembly parsing.
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The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:00:31 +00:00
Jim Grosbach
00a66653cb
ARM tests for EOR instruction parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:22:21 +00:00
Jim Grosbach
6a86feafa8
Remove duplicate tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:19:19 +00:00
Jim Grosbach
e77494e3e3
ARM Assembler support for DSB instruction.
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Add instalias for default 'sy' option. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:18:13 +00:00
Jim Grosbach
032434d622
ARM Assembler support for DMB instruction.
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Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:40:38 +00:00
Jim Grosbach
6f9f884502
ARM Assembler support for DBG instruction.
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Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:59:38 +00:00
Jim Grosbach
14ab1c3387
ARM parsing and encoding tests for CMN/CMP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:26:58 +00:00
Jim Grosbach
d986bc66bc
Shuffle ARM assembly tests a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:19:10 +00:00
Jim Grosbach
83ab070fc1
Range checking for CDP[2] immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Jim Grosbach
9bb098ad3a
Fix predicates for Thumb co-processor instructions.
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They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:14:23 +00:00
Jim Grosbach
f333d471d2
Testcases for ARM assembly BX/BXJ instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:25:46 +00:00
Jim Grosbach
37023b05c8
Testcases for ARM assembly BLX/BL instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:11:04 +00:00
Jim Grosbach
fff76ee7ef
Range checking for 16-bit immediates in ARM assembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:10:10 +00:00
Jim Grosbach
21101d60ce
Add tests for ARM parsing of 'BKPT' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:17:36 +00:00
Jim Grosbach
76cbe02cdd
Fix copy-pasto.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:16:30 +00:00
Jim Grosbach
e52240c370
Add tests for ARM parsing of 'BIC' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:12:32 +00:00
Jim Grosbach
7ed6d22e96
Add some FIXMEs.
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Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:10:23 +00:00
Jim Grosbach
59642c2600
Add tests for ARM parsing of 'AND' instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:55:14 +00:00
Jim Grosbach
19906729a4
Improve ARM assembly parsing diagnostics a bit.
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Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:49:30 +00:00
Jim Grosbach
da9f278c74
Add tests for ARM parsing of 'ADD' instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:12:46 +00:00
Jim Grosbach
37ee464ea9
Destination register operand is optional for ADC and SBC ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8
Flesh out ARM Parser support for shifted-register operands.
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Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:50:29 +00:00
Jim Grosbach
dc89561fec
Add check for predicate w/o S bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:25:04 +00:00
Jim Grosbach
3f00e31706
Fix recognition of ARM 'adcs' mnemonic.
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The 'CS' is not a predication suffix in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 17:09:57 +00:00
Jim Grosbach
589130fac1
Simplify printing of ARM shifted immediates.
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Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:48:36 +00:00
Evan Cheng
59ee62d241
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
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and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Evan Cheng
3286920505
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:36:29 +00:00
Evan Cheng
39dfb0ff84
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 03:55:05 +00:00
Kevin Enderby
d7c7e2ff7d
Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:55:20 +00:00
Kevin Enderby
d521f2d2f1
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
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push with a small constant produces a 2-byte push.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:23:46 +00:00