Commit Graph

92401 Commits

Author SHA1 Message Date
Richard Sandiford
af2a1bebfc [SystemZ] Tighten branch tests
After r182274, the branches in these tests must always be short.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 08:53:17 +00:00
Benjamin Kramer
f19b8b018b DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.
Fixes PR16083.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 08:51:09 +00:00
Richard Sandiford
275428fe4a Fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 08:48:24 +00:00
Eric Christopher
4b5c3f6094 Add cmake bits for md5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 01:30:38 +00:00
Eric Christopher
9f31f7c305 Add an md5 library derived from a public domain implementation for dwarf4
type signature computation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 01:28:35 +00:00
Reed Kotler
49d44a080a Add checks that the proper predeined stubs are being called to the test case.
These were accidentally omitted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182347 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 01:27:36 +00:00
Manman Ren
01cb18ea08 Dwarf: use a single line table to generate assembly when .loc is used.
This is to fix PR15408 where an undefined symbol Lline_table_start1 is used.
Since we do not generate the debug_line section when .loc is used,
Lline_table_start1 is not emitted and we can't refer to it when calculating
at_stmt_list for a compile unit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 00:57:22 +00:00
Reed Kotler
bf00bf9ad2 Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.

As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 00:50:30 +00:00
Richard Smith
6f43379e23 Comment update: these things are called "configuration names" these days, not
"triples". Also remove the implication that they're only used for specifying a
target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182335 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 23:55:41 +00:00
Sean Silva
57f429fcac LangRef.rst: Clarify how basic blocks without named label are handled.
Describe that they are assigned numbered label using the same counter
as for unnamed temporaries.

Based on http://llvm.org/bugs/show_bug.cgi?id=16043 and mailing list
discussion.

Patch by Paul Sokolovsky!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182332 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 23:31:12 +00:00
David Blaikie
7b72cc7782 PR14606: Debug Info for namespace aliases/DW_TAG_imported_module
This resolves the last of the PR14606 failures in the GDB 7.5 test
suite by implementing an optional name field for
DW_TAG_imported_modules/DIImportedEntities and using that to implement
C++ namespace aliases (eg: "namespace X = Y;").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 22:50:35 +00:00
Daniel Dunbar
ff2515ef2c [docs] Minor doc tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 22:39:48 +00:00
Bill Wendling
3b1040c703 The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like the other EH passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182321 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 21:54:18 +00:00
Bill Wendling
07418cde47 No need to store the TargetMachine variable in this class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 21:28:28 +00:00
Bill Wendling
d02c8f4066 Remove unused #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 20:59:12 +00:00
Hal Finkel
4e6b24ffcf Rename LoopSimplify.h to LoopUtils.h
As discussed, LoopUtils.h is a better name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 20:46:30 +00:00
Sebastian Pop
b02834cf1f add polly to check-all
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182308 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 18:49:15 +00:00
Akira Hatanaka
1aeb13bd9c [mips] Add (setne $lhs, 0) instruction selection pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 18:18:07 +00:00
Akira Hatanaka
f894199a14 [mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 18:07:43 +00:00
Hal Finkel
08f92c98ac Remove copied preheader insertion logic from PPCCTRLoops
Now that the preheader insertion logic in LoopSimplify is externally exposed,
use it, and remove the copy-and-pasted version.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:47:10 +00:00
Hal Finkel
fc32605ff3 Expose InsertPreheaderForLoop from LoopSimplify to other passes
Other passes, PPC counter-loop formation for example, also need to add loop
preheaders outside of the regular loop simplification pass. This makes
InsertPreheaderForLoop a global function so that it can be used by other
passes.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:47:07 +00:00
Justin Holewinski
9b39c726a0 [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182298 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:42:18 +00:00
Justin Holewinski
d223675593 [NVPTX] Add programmatic interface to NVVMReflect pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:42:16 +00:00
Hal Finkel
85c08b059c Rename PPC MTCTRse to MTCTRloop
As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182296 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:08:37 +00:00
Hal Finkel
e50c8c1f81 Add a PPCCTRLoops verification pass
When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.

In short, this is to help us sleep better at night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182295 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:08:17 +00:00
Benjamin Kramer
d54bf7ceef R600: Fix bug detected by GCC warning.
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:58:43 +00:00
Tom Stellard
4f8d90df45 R600: Fix rotr.ll on non-asserts builds
The -debug-only option is only available on asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:28:48 +00:00
Tom Stellard
5ad6d082fc R600/SI: Use a multiclass for MUBUF_Load_Helper
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:31 +00:00
Tom Stellard
307a84425c R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:28 +00:00
Tom Stellard
0bbfc9313c R600/SI: Add pattern for rotr
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:24 +00:00
Tom Stellard
ba534c2143 R600: Swap the legality of rotl and rotr
The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:19 +00:00
Tom Stellard
a9d5d0b346 R600/SI: Add patterns for 64-bit shift operations
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:12 +00:00
Tom Stellard
fbdd318120 R600/SI: Use the same names for VOP3 operands and encoding fields
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:08 +00:00
Tom Stellard
9bf4590aaa R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:01 +00:00
Mihai Popa
30a7a7c1fd VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:57:05 +00:00
Mihai Popa
bac932e9c3 Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:42:43 +00:00
Richard Sandiford
44b486ed78 [SystemZ] Add long branch pass
Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:23:08 +00:00
Benjamin Kramer
e932e891e5 Enable pod-like optimizations for pred and succ iterators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 13:12:58 +00:00
Justin Holewinski
7536ecf291 [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.

The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space.  Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 12:13:32 +00:00
Justin Holewinski
55fdf53629 [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 12:13:28 +00:00
Stepan Dyatkovskiy
083bc97344 PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:

Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack  ------ ...

FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.

We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.

This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 08:01:34 +00:00
Renato Golin
3a408fa878 Disable remote MCJIT on pre-v6 ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 07:46:06 +00:00
Bob Wilson
a4de3f2c85 Partially revert change in r181200 that tried to simplify JIT unit test #ifdefs.
The export list for this test requires the following symbols to be available:
  JITTest_AvailableExternallyFunction
  JITTest_AvailableExternallyGlobal
The change in r181200 commented them out, which caused the test to fail to
link, at least on Darwin. I have only reverted the change for arm, since I
can't test the other targets and since it sounds like that change was fixing
real problems for those other targets. It should be possible to rearrange the
code to keep those definitions outside the #ifdefs, but that should be done by
someone who can reproduce the problems that r181200 was trying to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 06:13:09 +00:00
Jakob Stoklund Olesen
89f530ebbf Also expand 64-bit bitcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
5e5b78ca36 Implement spill and fill of I64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
900622e099 Mark i64 SETCC as expand so it is turned into a SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 00:28:36 +00:00
Benjamin Kramer
4dc8bdf87d Replace some bit operations with simpler ones. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 22:01:57 +00:00
Jakob Stoklund Olesen
634123e98d Don't use %g0 to materialize 0 directly.
The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
60abcb786e Select i64 values with %icc conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:38:21 +00:00
Bob Wilson
2ed2ad00f9 Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>
This fixes a bootstrapping problem with builds for Apple ARM targets.
Clang had the wrong prototype for __clear_cache with ARM targets.  Rafael
fixed that in clang svn r181784 and r181810, but without those changes,
we can't build this code for ARM because clang reports an error about the
declaration in Memory.inc not matching the builtin declaration. Some of our
buildbots need to use an older compiler that doesn't have the clang fix.
Since __clear_cache is never used here when __APPLE__ is defined, I'm just
conditionalizing the declaration to match that. I also moved the declaration
of sys_icache_invalidate inside the conditional for __APPLE__ while I was at
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:33:51 +00:00