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4557 Commits

Author SHA1 Message Date
Davide Italiano
62df004d25 [tests] Use llvm-readobj instead of macho-dump. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243487 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-28 21:58:08 +00:00
Igor Breger
ec6000afc4 AVX512: Add encoding tests to vptestnm instructions 
Differential Revision: http://reviews.llvm.org/D11521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243391 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-28 07:00:00 +00:00
Igor Breger
e5dac1fb56 AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructions 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11528

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243390 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-28 06:53:28 +00:00
Igor Breger
6df163bcdf Implemented encoding and intrinsics of the following instructions 
vunpckhps/pd, vunpcklps/pd, 
  vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11509

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243246 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-26 14:41:44 +00:00
Igor Breger
a1692b30cb AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243122 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-24 17:24:15 +00:00
Michael Kuperstein
dedb07fcbe [X86] Fix order of operands for ins and outs instructions when parsing intel syntax 
Patch by: marina.yatsina@intel.com
Differential Revision: http://reviews.llvm.org/D11337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243001 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-23 10:23:48 +00:00
Chandler Carruth
0451957993 Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..." 
This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.

It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242992 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-23 08:03:44 +00:00
Igor Breger
cb8fe113a3 AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242990 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-23 07:39:21 +00:00
Asaf Badouh
717d8ad6cf [X86][AVX512] add reduce/range/scalef/rndScale 
include encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D11222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242896 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-22 12:00:43 +00:00
Michael Kuperstein
989e1eb99f Fix test from r242886 to use the right triple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242889 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-22 11:19:22 +00:00
Michael Kuperstein
93d5626c13 [X86] Add .intel_syntax noprefix directive to intel-syntax x86 asm output 
Patch by: michael.zuckerman@intel.com
Differential Revision: http://reviews.llvm.org/D11223

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242886 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-22 10:49:44 +00:00
Bruno Cardoso Lopes
a14dff356b [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRel 
Check whether BaseCst is valid before extracting a GlobalValue.
This fixes PR24163.

Patch by David Majnemer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242840 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-21 21:45:42 +00:00
Igor Breger
7d40c4215d AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11351

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242761 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-21 07:11:28 +00:00
Vasileios Kalintiris
1a71ee21d3 [mips] Added support for the ERETNC instruction. 
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242666 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-20 12:28:56 +00:00
Michael Kuperstein
00552e3875 [X86] Add support for tbyte memory operand size for Intel-syntax x86 assembly 
Differential Revision: http://reviews.llvm.org/D11257
Patch by: marina.yatsina@intel.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242639 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-19 11:03:08 +00:00
Benjamin Kramer
17351cfb43 [PPC] Disassemble little endian ppc instructions in the right byte order 
PR24122. The test is simply a byte swapped version of ppc64-encoding.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242288 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-15 12:56:19 +00:00
Petr Pavlu
ec223f1217 [AArch64] Fix problems in decoding generic MSR instructions 
Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-15 08:10:30 +00:00
Tim Northover
93398438ff AArch64: add rev64 alias for 64-bit rev instruction. 
It could be useful to assembly programmers and makes the permitted variants a
little more uniform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242164 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-14 17:07:29 +00:00
Daniel Sanders
815d6131a4 [mips] Fix li/la differences between IAS and GAS. 
Summary:
- Signed 16-bit should have priority over unsigned.
- For la, unsigned 16-bit must use ori+addu rather than directly use ori.
- Correct tests on 32-bit immediates with 64-bit predicates by
  sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000)
  should be true and use addiu.

Also split li/la testing into separate files due to their size.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242139 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-14 12:24:22 +00:00
David Majnemer
8a2d65cf4a [MC] Correctly escape .safeseh's symbol 
This fixes PR24107.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242050 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-13 18:51:15 +00:00
Scott Douglass
f8560e5a5b [ARM] Handle commutativity when converting to tADDhirr in Thumb2 
Also, run thumb_rewrite.s tests in Thumb2 now that they pass.

Differential Revision: http://reviews.llvm.org/D11132

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242036 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-13 15:31:48 +00:00
Scott Douglass
ffc51593c8 [ARM] Add Thumb2 ADD with SP narrowing from 3 operand to 2 
Differential Revision: http://reviews.llvm.org/D11131

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242035 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-13 15:31:40 +00:00
Scott Douglass
f716895679 [ARM] Small refactor of tryConvertingToTwoOperandForm (nfc) 
Also, add more Thumb2 ADD tests requested during review of
http://reviews.llvm.org/D11053.

Differential Revision: http://reviews.llvm.org/D11130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242034 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-13 15:31:33 +00:00
Elena Demikhovsky
a0a51734cd AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types. 
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.

Differential Revision: http://reviews.llvm.org/D11134



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242023 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-13 13:26:20 +00:00
David Majnemer
f2c71ff7a8 [llvm-objdump] Require that jump targets shown in -d are functions 
Don't let the disassembler pick call <.text> if a function happens to
live at the start of the section by only using function symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241830 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-09 18:11:40 +00:00
Scott Douglass
0e714c7efa [ARM] Thumb1 3 to 2 operand convertion for commutative operations 
Differential Revision: http://reviews.llvm.org/D11057

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241802 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-09 14:13:55 +00:00
Scott Douglass
7b8defda79 [ARM] Don't be overzealous converting Thumb1 3 to 2 operands 
Differential Revision: http://reviews.llvm.org/D11056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241801 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-09 14:13:48 +00:00
Scott Douglass
3ca1884ba8 [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2 
Differential Revision: http://reviews.llvm.org/D11055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241800 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-09 14:13:41 +00:00
Scott Douglass
ab17c04abe [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc) 
Also adds some test cases.

Differential Revision: http://reviews.llvm.org/D11054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241799 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-09 14:13:34 +00:00
Scott Douglass
c221d448c7 [ARM] Add ADD tests for Thumb2 narrowing (nfc) 
Differential Revision: http://reviews.llvm.org/D11053

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241798 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-09 14:13:22 +00:00
David Majnemer
b99ee32499 [llvm-objdump] Print the call target next to the instruction 
GNU binutils provides this behavior.  objdump -r doesn't really help
when you aren't dealing with relocation object files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241631 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-07 22:06:59 +00:00
James Y Knight
067b86fcab [Sparc] Add more instruction aliases. 
These are mostly from the chart in the SparcV8 spec, section "A.3
Synthetic Instructions".

Differential Revision: http://reviews.llvm.org/D9834

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241461 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-06 16:01:07 +00:00
James Y Knight
d32974f9dc [Sparc] Add support for flush instruction. 
Differential Revision: http://reviews.llvm.org/D9833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241460 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-06 16:01:04 +00:00
Asaf Badouh
169ee3383c [X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale 
pmulhrsw

review:
http://reviews.llvm.org/D10948

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241443 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-06 14:03:40 +00:00
Asaf Badouh
5047893c31 [x86][AVX512] add Multiply High Op 
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241406 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-05 12:23:20 +00:00
Michael Kuperstein
bb803fd76e [X86] Fix incorrect/inefficient pushw encodings for x86-64 targets 
Correctly support assembling "pushw $imm8" on x86-64 targets. 
Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually
represent the same instruction)

This fixes PR23996

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241404 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-05 10:25:41 +00:00
Craig Topper
9a9ee6f550 [X86] Add proper 64-bit mode checks to jrcxz and jcxz. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241381 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-04 00:01:07 +00:00
Gabor Ballabas
4e0f6008b9 Reworking the test part of r241149 
The test part of r241149 has been reverted in r241451, due to misplaced test cases.
This patch splits those test cases among the appropriate targets.

Differential Revision: http://reviews.llvm.org/D10897


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241283 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-02 16:53:23 +00:00
Michael Kuperstein
7edba9eec3 [X86] Convert an instruction relaxation test to use objdump instead of readobj 
Patch by: david.l.kreitzer@intel.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241270 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-02 14:27:35 +00:00
Arnaud A. de Grandmaison
bdaa375556 [AArch64] Implement add/adds/sub/subs/cmp/cmn with negative immediate aliases 
This patch teaches the AsmParser to accept add/adds/sub/subs/cmp/cmn
with a negative immediate operand and convert them as shown:

  add  Rd, Rn, -imm -> sub  Rd, Rn, imm
  sub  Rd, Rn, -imm -> add  Rd, Rn, imm
  adds Rd, Rn, -imm -> subs Rd, Rn, imm
  subs Rd, Rn, -imm -> adds Rd, Rn, imm
  cmp  Rn, -imm     -> cmn  Rn, imm
  cmn  Rn, -imm     -> cmp  Rn, imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers (gas). They are documented in the "ARMv8 Instruction Set
Overview", in the "Arithmetic (immediate)" section. This makes llvm-mc
a programmer-friendly assembler !

This also fixes PR20978: "Assembly handling of adding negative numbers
not as smart as gas".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241166 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 15:05:58 +00:00
Igor Breger
2ae30810d8 AVX-512: Implemented missing encoding for FMA scalar instructions 
Added tests for encoding

Differential Revision: http://reviews.llvm.org/D10865

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241159 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 13:24:28 +00:00
Michael Kuperstein
5020a9198d [X86] Avoid over-relaxation of 8-bit immediates in integer arithmetic instructions. 
Only consider an instruction a candidate for relaxation if the last operand of the 
instruction is an expression. We previously checked whether any operand is an expression,
which is useless, since for all instructions concerned, the only operand that may be
affected by relaxation is the last one.
In addition, this removes the check for having RIP as an argument, since it was 
plain wrong - even when one of the arguments is RIP, relaxation may still be needed.

This fixes PR9807.

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241152 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 10:54:42 +00:00
NAKAMURA Takumi
275fa93acf Revert part of r241149, "Fix PR23872: Integrated assembler error message when using .type directive with @ in AArch32 assembly." 
The test should be split among targets. llvm/test/MC/ELF/ is assumed as X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241151 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 10:28:09 +00:00
Zoran Jovanovic
627c5342b2 [mips][microMIPS] Implement SLL and NOP instructions 
http://reviews.llvm.org/D10474


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241150 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 09:54:51 +00:00
Gabor Ballabas
9f9bf86ed5 Fix PR23872: Integrated assembler error message when using .type directive with @ in AArch32 assembly. 
The AArch32 assembler parses the '@' as a comment symbol, so the error message shouldn't suggest
that '@<type>' is a valid replacement when assembling for AArch32 target.

Differential Revision: http://reviews.llvm.org/D10651 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241149 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 08:58:49 +00:00
Toma Tabacu
e143a3abc2 [mips] [IAS] Add support for the .module softfloat/hardfloat directives. 
These directives are used to set the default value of the SoftFloat feature.
They have the same effect as setting -m{soft, hard}-float from the command line.

Differential Revision: http://reviews.llvm.org/D9073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241066 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-30 13:46:03 +00:00
Toma Tabacu
dcec5265ae [mips] [IAS] Make .module directives change AssemblerOptions->front(). 
Differential Revision: http://reviews.llvm.org/D10643

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241062 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-30 12:41:33 +00:00
Toma Tabacu
5dee8da754 [mips] [IAS] Add support for the .set oddspreg/nooddspreg directives. 
Differential Revision: http://reviews.llvm.org/D10657

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241052 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-30 09:36:50 +00:00
Elena Demikhovsky
546178bfe5 AVX-512: all forms of SCATTER instruction on SKX, 
encoding, intrinsics and tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240936 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-29 12:14:24 +00:00
Javed Absar
263dd533ee [ARM]: Extend -mfpu options for half-precision and vfpv3xd 
Some of the the permissible ARM -mfpu options, which are supported in GCC,
are currently not present in llvm/clang.This patch adds the options:
'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16.
These are related to half-precision floating-point and single precision.

Reviewers: rengolin, ranjeet.singh

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10645



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240930 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-29 09:32:29 +00:00