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306 Commits

Author SHA1 Message Date
Bill Wendling
3f3a17dd62 Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers 
clobbered by a call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36448 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 21:31:48 +00:00
Lauro Ramos Venancio
ede1d78969 X86 TLS: optimize the implementation of "local exec" model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36359 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 01:28:10 +00:00
Lauro Ramos Venancio
7d2cc2b983 X86 TLS: fix and optimize the implementation of "initial exec" model. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36355 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-22 22:50:52 +00:00
Lauro Ramos Venancio
b3a0417cad Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:38:10 +00:00
Anton Korobeynikov
57fc00d5cf Implemented correct stack probing on mingw/cygwin for dynamic alloca's. 
Also, fixed static case in presence of eax livin. This fixes PR331

PS: Why don't we still have push/pop instructions? :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36195 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 09:20:00 +00:00
Bill Wendling
bb1ee05253 Add support for our first SSSE3 instruction "pmulhrsw". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-10 22:10:25 +00:00
Evan Cheng
768143547b Mark re-materializable instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35230 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-21 00:16:56 +00:00
Jim Laskey
1ee2925742 Make LABEL a builtin opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-26 14:34:52 +00:00
Chris Lattner
d06b2ab701 Fix a misencoding of CBW and CWD. This fixes PR1030. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33486 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-24 18:31:00 +00:00
Evan Cheng
28b51439f3 - Switch X86-64 JIT to large code size model. 
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32238 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-05 19:50:18 +00:00
Evan Cheng
0085a28d13 - Use a different wrapper node for RIP-relative GV, etc. 
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32046 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-30 21:55:46 +00:00
Evan Cheng
3fa9dff2c9 Custom lower READCYCLECOUNTER for x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32017 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-29 08:28:13 +00:00
Chris Lattner
3751844b39 remove dead/redundant vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31435 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 23:48:56 +00:00
Reid Spencer
02b8511364 Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4 
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31299 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 22:32:30 +00:00
Evan Cheng
8b2794aeff Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-13 21:14:26 +00:00
Chris Lattner
33e4869ba0 Move the Imp tblgen class from the X86 backend to common code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30907 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-12 17:49:27 +00:00
Chris Lattner
f18c074e1b Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice 
that it can't assume ESP is unmodified across the instrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30905 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-12 17:42:56 +00:00
Evan Cheng
af9db75943 Add properties to ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-11 21:03:53 +00:00
Evan Cheng
466685d41a Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-09 20:57:25 +00:00
Evan Cheng
f10c17f986 Delete dead code; fix 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30583 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-22 21:43:59 +00:00
Evan Cheng
734503be59 X86ISD::CMP now produces a chain as well as a flag. Make that the chain 
operand of a conditional branch to allow load folding into CMP / TEST
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30241 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 02:19:56 +00:00
Evan Cheng
25ab690a43 Committing X86-64 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 06:48:29 +00:00
Chris Lattner
ffc0b2663e Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns 
using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30156 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 20:33:45 +00:00
Evan Cheng
ec3bc39413 Consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30152 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 19:03:48 +00:00
Evan Cheng
bb7b844bec CALLSEQ_* produces chain even if that's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:03:33 +00:00
Evan Cheng
cbac2fa23a Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29228 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-20 21:37:39 +00:00
Evan Cheng
1693e489e6 INC / DEC instructions have shorter code size than ADD32ri8, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29194 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 00:27:29 +00:00
Evan Cheng
f7eb5d0b02 Emit inc / dec of registers as one byte instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29110 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 19:49:49 +00:00
Evan Cheng
09c545790d Add shift and rotate by 1 instructions / patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28980 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-29 00:36:51 +00:00
Evan Cheng
4df24f2caf Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28938 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-27 20:34:14 +00:00
Evan Cheng
fae2994302 X86 call instructions can take variable number of operands. Parameters of 
vector types are passed via XMM registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28789 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-14 22:24:55 +00:00
Evan Cheng
94b1453278 Incorrect AT&T opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28666 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-02 21:09:10 +00:00
Evan Cheng
cbe70e1c4b Rename ASM modifier trunc8, trunc16 to subreg8, subreg16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28606 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-31 22:34:26 +00:00
Evan Cheng
f91c10153c Sign extender 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-31 22:05:11 +00:00
Evan Cheng
e6ad27e917 A addressing mode folding enhancement: 
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
  return (x << 3) + 7;
}

This can be codegen'd as:
leal 7(,%eax,8), %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28550 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-30 06:59:36 +00:00
Evan Cheng
fb914c43ba Remove unused patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28417 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-20 01:40:16 +00:00
Evan Cheng
09e3c80984 - Use exact-width integer types, e.g. int32_t, to avoid confusion. 
- Fix a couple of minor bugs in i16immSExt8 and i16immZExt8.
- Added loadiPTR fragment used for indirect jumps and calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28392 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-19 18:40:54 +00:00
Evan Cheng
fc8feb184e Explicitly specify MOV32mi can only be used store 32-bit GV, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28390 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-19 07:30:36 +00:00
Evan Cheng
af78ef526d Use generic iPTR instead i32 to represent pointer type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-17 21:21:41 +00:00
Evan Cheng
069287d460 X86 integer register classes naming changes. Make them consistent with FP, vector classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-16 07:21:53 +00:00
Evan Cheng
403be7eafc Fixing truncate. Previously we were emitting truncate from r16 to r8 as 
movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-08 08:01:26 +00:00
Evan Cheng
4713724eda Need extload patterns after Chris' DAG combiner changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28127 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 08:23:07 +00:00
Evan Cheng
8f7f7125e9 Better implementation of truncate. ISel matches it to a pseudo instruction 
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28119 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-05 05:40:20 +00:00
Evan Cheng
fea89c14ec Make x86 isel lowering produce tailcall nodes. They are match to normal calls 
for now.

Patch contributed by Alexander Friedman.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27994 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-27 08:40:39 +00:00
Nate Begeman
a766765358 Optimized stores to the constant pool, while cool, are unnecessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27948 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 22:31:45 +00:00
Nate Begeman
37efe67645 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 18:53:45 +00:00
Evan Cheng
11e15b38e9 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. 
- Some bug fixes and naming inconsistency fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27377 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-03 20:53:28 +00:00
Evan Cheng
6e16ee5634 Added missing (any_extend (load ...)) patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27120 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-25 09:45:48 +00:00
Chris Lattner
29b4dd0c9c Fix the encodings of these new instructions, hopefully fixing the JIT 
failures from last night


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26981 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 16:13:50 +00:00
Nate Begeman
ce9448218a Add support for 8 bit immediates with 16/32 bit cmp instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26966 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-23 01:29:48 +00:00