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c9792a3c1f
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14804 Commits

Author SHA1 Message Date
Jim Grosbach
c9792a3c1f Cosmetic cleanup. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:51:20 +00:00
Jim Grosbach
5caeff5c01 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:37:40 +00:00
Bob Wilson
13ef840807 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed 
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 00:27:15 +00:00
Jim Grosbach
0798eddd07 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:49:24 +00:00
Evan Cheng
12616727c7 Use report_fatal_error, not llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:45:31 +00:00
Jim Grosbach
a65850230a back out 104862/104869. Can reuse stacksave after all. Very cool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:11:57 +00:00
Evan Cheng
84f60b7359 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 22:08:38 +00:00
Kevin Enderby
bd658918df MC/X86: Add aliases for Jcc variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 21:33:19 +00:00
Bob Wilson
d984eb6073 Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases 
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 20:23:42 +00:00
Dale Johannesen
54feef2950 Mark some math lib intrinsic nodes Legal on SSE4.1. 
No functional effect as these nodes are not generated yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 20:12:41 +00:00
Dan Gohman
4d3d6e1a0c FastISel doesn't yet handle callee-pop functions. 
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:43:40 +00:00
Jim Grosbach
ad9aaf038e add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:23:48 +00:00
Bruno Cardoso Lopes
aa02ff1a2b Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring 
common code between SSE versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:17:40 +00:00
Daniel Dunbar
dcbab9cf5a AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected 
to be matched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 22:21:28 +00:00
Jakob Stoklund Olesen
c8b9f6ce23 Give SubRegIndex names to all ARM subregisters. This will be required by 
TableGen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 22:15:03 +00:00
Daniel Dunbar
cb8326dc09 MC: Add TargetMachine support for setting the value of MCRelaxAll with 
-filetype=obj.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
160a3bf74d Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 21:47:28 +00:00
Jim Grosbach
23ff7cff52 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 20:22:18 +00:00
Kevin Enderby
b106543592 Fix the x86 move to/from segment register instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 20:10:45 +00:00
Daniel Dunbar
95506d40c5 MC: Change RelaxInstruction to only take the input and output instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 18:15:06 +00:00
Dan Gohman
d9c2af5409 Fix a typo in a comment that Gabor noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 18:03:53 +00:00
Daniel Dunbar
8488252855 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it 
before encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen
ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 17:27:12 +00:00
Daniel Dunbar
c90e30aa6f MC: Eliminate MCAsmFixup, replace with MCFixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104699 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 15:18:56 +00:00
Daniel Dunbar
482ad802f1 MC: Use accessors for access to MCAsmFixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 15:18:31 +00:00
Daniel Dunbar
c9adb8c61e MC: Change MCInst::dump_pretty to not include a trailing newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104696 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 15:18:13 +00:00
Zhongxing Xu
c2798a18a7 SRetReturnReg was set in LowerFormalArguments(). So only assert it here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104691 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 08:10:02 +00:00
Shih-wei Liao
9f3b6a381a Coding style change (Adding 1 missing space.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 04:46:50 +00:00
Shih-wei Liao
45469f38b6 Adding the missing implementation for ARM::SBFX and ARM::UBFX. 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 03:21:39 +00:00
Jim Grosbach
54e13eceff fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:22:21 +00:00
Jakob Stoklund Olesen
b555609e73 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:28:19 +00:00
Shih-wei Liao
6d37a29588 Adding the missing implementation of Bitfield's "clear" and "insert". 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143 To handle s* registers in emitVFPLoadStoreMultipleInstruction(). 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:02:28 +00:00
Jakob Stoklund Olesen
76f0ad7bf5 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 23:43:18 +00:00
Kevin Enderby
cf50a5390c Changed the encoding of X86 floating point stack operations where both operands 
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 20:52:34 +00:00
Jakob Stoklund Olesen
b53985239c Separate unrelated cases that once shared a numeric value 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:40 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
4fda9670f0 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:33 +00:00
Daniel Dunbar
39e2dd7bab MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:32 +00:00
Daniel Dunbar
79373680ed MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9 The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 18:16:58 +00:00
Eric Christopher
7e2f5aaa67 Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
48d0c163fb Ignore NumberHack and give each SubRegIndex instance a unique enum value instead. 
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
c159fba712 Use enums instead of literals for SystemZ subregisters 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:04:18 +00:00
Jakob Stoklund Olesen
22c0e97c56 Use enums instead of literals for X86 subregisters. 
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:04:16 +00:00
Zonr Chang
f3c770a2cb Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate)) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c Add support to MOVimm32 using movt/movw for ARM JIT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 08:42:45 +00:00
Bob Wilson
a85df80ed7 Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. 
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e Fix up instruction classes for Thumb2 RSB instructions to be consistent with 
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 04:43:08 +00:00