Owen Anderson
cd00dc6852
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:28:46 +00:00
Bruno Cardoso Lopes
457d53d9ce
Revert the wrong part of r139528, and fix testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 21:24:07 +00:00
Owen Anderson
fd92d2e106
Fix encoding of PC-relative LDRSHW with an immediate offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 20:36:51 +00:00
Andrew Trick
26e5285f9f
Conditionalize indvars tests that rely on SCEV expansion of geps,
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which is relevant with canonical IVs. Anything else being checked by
these tests is already covered by early CSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 20:26:34 +00:00
Bruno Cardoso Lopes
8e03a821f9
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
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However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 19:30:40 +00:00
Owen Anderson
a3157b4026
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:56:30 +00:00
Andrew Trick
29da5e6855
Removing indvars tests that directly test canonical IVs and nothing else.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:33:08 +00:00
Andrew Trick
f21bdf4f42
Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:28:44 +00:00
Eli Friedman
9f3b6a5a2a
Fix mistake in test runline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 17:32:58 +00:00
Andrew Trick
8f7ca5d98e
Test case for r139453, WidenIV::GetExtendedOperandRecurrence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139504 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 17:20:57 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Craig Topper
136046c9a2
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
Craig Topper
038197988b
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 21:41:45 +00:00
Craig Topper
842f58f9be
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 20:23:20 +00:00
Eli Friedman
cfeb55cdbc
Really un-XFAIL the testcase, like I said I would in r139458.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:02:27 +00:00
Richard Trieu
2db8628085
Fixed an assert from:
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assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Jim Grosbach
1ad60c2adc
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 00:15:36 +00:00
Akira Hatanaka
33ff5aeaa8
Fix test cases.
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Generate code for Mips32r1 unless a Mips32r2 feature is tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:14:58 +00:00
Owen Anderson
921d01ae1f
LDM writeback is not allowed if Rn is in the target register list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:33 +00:00
Owen Anderson
08fef885eb
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:48:23 +00:00
Eli Friedman
9db817fd0c
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8
Drop support for Mips1 and Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:29:17 +00:00
Jim Grosbach
468709e43d
Thumb2 assembly parsing and encoding for MLA and MLS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:24:45 +00:00
Jim Grosbach
84d043a8b3
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:19:28 +00:00
Jim Grosbach
1e0fff17f3
Tidy up formatting a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:17:49 +00:00
Jim Grosbach
95102265a9
Thumb2 assembly parsing and encoding for LSL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:05:38 +00:00
Jim Grosbach
d4b72de3e2
Thumb2 assembly parsing and encoding for LDRT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:02:15 +00:00
Jim Grosbach
56806c2997
Thumb2 assembly parsing and encoding for LDRSHT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:01:18 +00:00
Jim Grosbach
a315a99093
Thumb2 assembly parsing and encoding for LDRSH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:54:30 +00:00
Jim Grosbach
578edfbfa0
Thumb2 assembly parsing and encoding for LDRSBT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:49:06 +00:00
Jim Grosbach
0811fe13d6
Thumb2 assembly parsing and encoding for LDRSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:42:40 +00:00
Jim Grosbach
95d397c3b1
Thumb2 assembly parsing and encoding for LDRH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:13:53 +00:00
Jim Grosbach
1efd9a0e8b
Shuffle a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139385 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:09:54 +00:00
Akira Hatanaka
d199d0c59c
Drop support for Allegrex. Allegrex implements a variant of Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Jim Grosbach
b6aed508e3
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Jim Grosbach
e3a0adf162
Add FIXME.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 16:45:31 +00:00
Duncan Sands
73c8415d90
Mark the eh.typeid.for intrinsic as being 'const', which it is inside
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any given function. As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 07:50:37 +00:00
Craig Topper
d3be6ecafe
Add disassembler test for Intel syntax. Tests r139353.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 06:35:44 +00:00
Akira Hatanaka
ad5f0c9e73
Change default target architecture from Mips1 to Mips32r1 in preparation for
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removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 01:13:27 +00:00
Devang Patel
9aee335c23
Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:59:09 +00:00
Owen Anderson
d2fc31b3f7
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
7ec8fb8830
Add a AVX version of a simple i64 -> f64 bitcast. This could be
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triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
7cf79a88c8
Reapply testcase from r139309!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:05:43 +00:00
Kevin Enderby
5afc19002e
Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom
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without a base symbol that must not have a relocation entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 20:53:44 +00:00
Bruno Cardoso Lopes
caa60f15e4
Remove this crashing test, until I figure out what's going wrong here
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
814c6ced85
Add AVX versions of blend vector operations and fix some issues noticed
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in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 18:05:02 +00:00