Commit Graph

54 Commits

Author SHA1 Message Date
John Thompson
44ab89eb37 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 17:29:13 +00:00
Kalle Raiskila
8a52fa674b Implement two virtual functions in SPUTargetLowering.
Before the implementation of isLegalAddressingMode, some rare cases 
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a 
bad TargetLowering, or if the bug is elsewhere and this patch just 
hides it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:24:35 +00:00
Kalle Raiskila
f53fdc2e45 Remove some dead code from SPU BE that remained
from 64bit vector support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 11:05:51 +00:00
Kalle Raiskila
99534bb81a Have SPU handle halfvec stores aligned by 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 16:33:00 +00:00
Dan Gohman
c9403659a9 Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 15:54:55 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 21:55:36 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 15:26:15 +00:00
Evan Cheng
022d9e1cef Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 23:55:14 +00:00
Evan Cheng
942619695f Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 21:29:10 +00:00
Evan Cheng
0c439eb2c8 Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-27 00:07:07 +00:00
Sandeep Patel
65c3c8f323 Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-02 08:44:58 +00:00
Scott Michel
f1fa4fd282 128-bit sign extension and vector shift cleanups, contributed by Ken Werner
(IBM).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-24 22:28:53 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Owen Anderson
77547befdc Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 18:56:59 +00:00
Dan Gohman
98ca4f2a32 Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
Tilmann Scheller
667ee3cb43 Small cleanups in the PowerPC backend.
Small refactoring in LowerFORMAL_ARGUMENTS().
Correct minor formatting issues.
Remove size argument of CreateCopyOfByValArgument().
Remove dead argument from CalculateStackSlotSize().
Remove unused variable ReturnAddrIndex from various targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74763 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 06:43:35 +00:00
Bill Wendling
b4202b84d7 Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 18:50:55 +00:00
Bill Wendling
20c568f366 Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.

This allows for future work that would allow for precise no-op placement and the
like.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30 22:38:32 +00:00
Scott Michel
7ea02ffe91 CellSPU:
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17 01:15:45 +00:00
Dale Johannesen
ed2eee63a6 Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode.  Lots of
caller changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 01:31:28 +00:00
Scott Michel
c9c8b2a804 CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 03:31:40 +00:00
Scott Michel
d1e8d9c0a5 CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21 04:58:48 +00:00
Scott Michel
94bd57e154 - Convert remaining i64 custom lowering into custom instruction emission
sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
  DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
  that stretches tblgen and the imagination, as well as violating laws of
  several small countries and most southern US states (just kidding, but
  looking at a function with 80+ parameters is really weird and just plain
  wrong.)
- Update tests as needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15 04:41:47 +00:00
Scott Michel
21213e75b5 CellSPU:
- Add preliminary support for v2i32; load/store generates the right code but
  there's a lot work to be done to make this vector type operational.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61829 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-06 23:10:38 +00:00
Duncan Sands
5480c0469e Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-01 15:52:00 +00:00
Scott Michel
02d711b93e - Start moving target-dependent nodes that could be represented by an
instruction sequence and cannot ordinarily be simplified by DAGcombine
  into the various target description files or SPUDAGToDAGISel.cpp.

  This makes some 64-bit operations legal.

- Eliminate target-dependent ISD enums.

- Update tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-30 23:28:25 +00:00
Scott Michel
f0569be4a9 - Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
  needed. Consequently, the CellSPU backend would produce correct, but _really
  slow and horrible_, code.

  Replaced with instruction sequences that do the equivalent truncation in
  SPUInstrInfo.td.

- Re-examine how unaligned loads and stores work. Generated unaligned
  load code has been tested on the CellSPU hardware; see the i32operations.c
  and i64operations.c in CodeGen/CellSPU/useful-harnesses.  (While they may be
  toy test code, it does prove that some real world code does compile
  correctly.)

- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
  fault because i64 ult is not yet implemented.)

- Added i64 eq and neq for setcc and select/setcc; started new instruction
  information file for them in SPU64InstrInfo.td. Additional i64 operations
  should be added to this file and not to SPUInstrInfo.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-27 04:51:36 +00:00
Scott Michel
30ee7df71c CellSPU:
- First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch
  fixes sign/zero/any-extending loads for integers and floating point. Example
  code, compiled w/o debugging or optimization where he first noticed the bug:

  int main(void) {
    float a = 99.0;
    printf("%d\n", a);
    return 0;
  }

  Verified that this code actually works on a Cell SPU.

Changes by Scott Michel:
- Fix bug in the value type list constructed by SPUISD::LDRESULT to include
  both the load result's result and chain, not just the chain alone.
- Simplify LowerLOAD and remove extraneous and unnecessary chains.
- Remove unused SPUISD pseudo instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-04 03:02:42 +00:00
Duncan Sands
1607f05cb7 Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-01 11:39:25 +00:00
Scott Michel
104de4390b CellSPU:
(a) Improve the extract element code: there's no need to do gymnastics with
    rotates into the preferred slot if a shuffle will do the same thing.
(b) Rename a couple of SPUISD pseudo-instructions for readability and better
    semantic correspondence.
(c) Fix i64 sign/any/zero extension lowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59965 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24 17:11:17 +00:00
Scott Michel
7a1c9e9cb7 CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was it
ever conceived to occur).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59891 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-22 23:50:42 +00:00
Scott Michel
73ce1c513f CellSPU: Fix bug 3606, as well as some ongoing work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59009 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-10 23:43:06 +00:00
Dan Gohman
6520e20e4f Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
Evan Cheng
da43bcf624 Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24 00:05:32 +00:00
Dan Gohman
0ba2bcfcc3 Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56497 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-23 18:42:32 +00:00
Dan Gohman
475871a144 Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-27 21:46:04 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Scott Michel
8bf61e8c2a Add necessary 64-bit support so that gcc frontend compiles (mostly). Current
issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-02 22:18:03 +00:00
Scott Michel
203b2d6eed Bug fixes and updates for CellSPU, syncing up with trunk. Most notable
fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50462 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 00:30:08 +00:00
Chris Lattner
2ba1c06d48 no need to implement this method and just have it call
the default impl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50311 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-26 22:59:59 +00:00
Scott Michel
78c47fa50b Integer comparison tests for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 16:58:52 +00:00
Scott Michel
5b8f82e35b Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 15:42:14 +00:00
Scott Michel
a59d469e9b Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-23 18:41:37 +00:00
Nate Begeman
ccef580583 Fix single precision FP constants on SPU. They are actually legal,
which allows us to kill a target-specific node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47127 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-14 18:43:04 +00:00
Dan Gohman
977a76fbb6 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 22:28:48 +00:00
Dan Gohman
fd29e0eb06 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 00:35:47 +00:00
Evan Cheng
ff9b373e8f Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-30 18:18:23 +00:00
Scott Michel
7f9ba9bb3c More cleanups for CellSPU:
- Expand tabs... (poss 80-col violations, will get them later...)
- Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single
  function, simplifying maintenance. Also reduced custom instruction
  generation for SPUvecinsert/INSERT_MASK.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46544 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-30 02:55:46 +00:00
Scott Michel
053c1da8d9 Overhaul Cell SPU's addressing mode internals so that there are now
only two addressing mode nodes, SPUaform and SPUindirect (vice the
three previous ones, SPUaform, SPUdform and SPUxform). This improves
code somewhat because we now avoid using reg+reg addressing when
it can be avoided. It also simplifies the address selection logic,
which was the main point for doing this.

Also, for various global variables that would be loaded using SPU's
A-form addressing, prefer D-form offs[reg] addressing, keeping the
base in a register if the variable is used more than once.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29 02:16:57 +00:00