6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-05 13:09:10 +00:00
Code Issues Projects Releases Wiki Activity
62,464 Commits 39 Branches 0 Tags 277 MiB
db89809037
Commit Graph

10304 Commits

Author SHA1 Message Date
Evan Cheng
db89809037 Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108304 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 01:22:19 +00:00
Bob Wilson
9e82bf12a0 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. 
Radar 7373643.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-14 01:22:12 +00:00
Bruno Cardoso Lopes
7dbf7d8b1c Add AVX 256-bit compare instructions and a bunch of testcases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 22:06:38 +00:00
Bob Wilson
cba270d042 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent 
NEON VMOV-immediate instructions.  This simplifies some things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 21:16:48 +00:00
Bruno Cardoso Lopes
87a85c7ef0 AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 21:07:28 +00:00
Dale Johannesen
b5611a6230 In inline asm treat indirect 'X' constraint as 'm'. 
This may not be right in all cases, but it's better
than asserting which it was doing before.  PR 7528.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108268 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 20:17:05 +00:00
Dan Gohman
9dc8ae110f Add support for empty named metadata too. This isn't particularly 
useful, but it is nice for consistency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 19:42:44 +00:00
Dan Gohman
ac80975ea4 Add support for empty metadata nodes: !{}. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 19:33:27 +00:00
Evan Cheng
218977b53e Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 19:27:42 +00:00
Evan Cheng
ea4cdb7ead -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 18:46:14 +00:00
Dale Johannesen
24bb7bdb1e Fix PR number. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 18:14:47 +00:00
Duncan Sands
d0d3ccc827 Handle the case of a tail recursion in which the tail call is followed 
by a return that returns a constant, while elsewhere in the function
another return instruction returns a different constant.  This is a
special case of accumulator recursion, so just generalize the existing
logic a bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 15:41:41 +00:00
Chris Lattner
37a746bc85 my work on adding segment registers to LEA missed the 
disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 04:23:55 +00:00
Bruno Cardoso Lopes
fd920fa59a Add AVX 256-bit packed logical forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
6991623dd7 Add AVX 256-bit unop arithmetic instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
a0d09a85e2 Add AVX 256 binary arithmetic instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 23:04:15 +00:00
Dan Gohman
cfbf0ed8b0 Apply the SSE dependence idiom for SSE unary operations to 
SD instructions too, in addition to SS instructions. And
add a comment about it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 20:46:04 +00:00
Bruno Cardoso Lopes
aa099be71f Add AVX 256-bit MOVMSK forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 20:06:32 +00:00
Daniel Dunbar
b6c3a607ac MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108180 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 19:37:35 +00:00
Daniel Dunbar
492b7a21cb MC/AsmParser: Move .desc parsing to Darwin specific parser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 19:22:53 +00:00
Daniel Dunbar
9ac66b008d MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 18:49:22 +00:00
Dan Gohman
545d00645c Add a lint check for mismatched return types, inspired by PR6944. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108162 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 18:02:04 +00:00
Benjamin Kramer
c9fe6374b7 Nope, still breaks the release selfhost bots :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108153 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 16:38:48 +00:00
Benjamin Kramer
8fd437c43f Reapply the "or" half of r108136, which seems to be less problematic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 16:15:48 +00:00
Benjamin Kramer
e2d07b5208 Revert r108141 again, sigh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108148 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 14:42:04 +00:00
Benjamin Kramer
98a8206e58 Reapply 108136 with an ugly pasto fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108141 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 13:44:00 +00:00
Benjamin Kramer
0cc4ed1ca5 Revert r108136 until I figure out why it broke selfhost. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108139 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 12:35:49 +00:00
Benjamin Kramer
4fc719e607 instcombine: fold (x & y) | (~x & z) and (x & y) ^ (~x & z) into ((y ^ z) & x) ^ z which is one instruction shorter. (PR6773) 
before:
  %and = and i32 %y, %x
  %neg = xor i32 %x, -1
  %and4 = and i32 %z, %neg
  %xor = xor i32 %and4, %and

after:
  %xor1 = xor i32 %z, %y
  %and2 = and i32 %xor1, %x
  %xor = xor i32 %and2, %z


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 11:54:45 +00:00
Chris Lattner
dfd3626b47 fix PR7311 by avoiding breaking casts when a bitcast from scalar->vector 
is involved.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108117 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 01:19:22 +00:00
Chris Lattner
0a96144aac if jump threading is able to infer interesting values on both 
the LHS and RHS of an and/or instruction, don't multiply add
known predecessor values.  This fixes the crash on testcase
from PR7498


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 00:47:34 +00:00
Chris Lattner
eae2895120 fix PR7429, a crash turning a load from a string into a float. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108113 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 00:22:51 +00:00
Chris Lattner
ddef83536c convert to filechecconvert to filecheckk 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 00:21:10 +00:00
Chris Lattner
243a73d0e6 merge two tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-12 00:19:47 +00:00
Jakob Stoklund Olesen
744b3a5acd Remove TargetInstrInfo::copyRegToReg entirely. 
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 17:01:17 +00:00
Rafael Espindola
cbeeae23c3 Fix va_arg for doubles. With this patch VAARG nodes always contain the 
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 04:01:49 +00:00
Dan Gohman
e695de0c5f Fix this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 22:42:12 +00:00
Jakob Stoklund Olesen
5d6f892197 FileCheckize inline asm FP stack tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108046 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 16:30:25 +00:00
Dan Gohman
44dafc703c Add an explicit triple to make this test behave consistently. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 09:01:35 +00:00
Dan Gohman
6536132fac Fix this XTARGET so that this does doesn't XPASS on non-darwin hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108040 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 09:01:03 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32: 
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 09:00:22 +00:00
Bruno Cardoso Lopes
d52e78efac Add AVX 256-bit packed MOVNT variants 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
2bfb8f6ef8 Add AVX 256-bit unpack and interleave 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 21:20:35 +00:00
Jakob Stoklund Olesen
9c50e8b890 Fix a few tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 20:43:09 +00:00
Jim Grosbach
6c7d3a16b3 In the presence of variable sized objects, allocate an emergency spill slot. 
rdar://8131327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 20:27:06 +00:00
Dan Gohman
f870e566ee Add a target triple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108003 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 19:17:36 +00:00
Dan Gohman
aa7426070d Fix MachineLICM to actually visit inner loops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 18:49:45 +00:00
Bruno Cardoso Lopes
e86b01c153 Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 18:27:43 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.': 
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 16:37:18 +00:00
Jakob Stoklund Olesen
cfcb2f6898 Fix test to be less sensitive of regalloc accidents 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 01:32:11 +00:00
Bob Wilson
a0148c360e Print "dregpair" NEON operands with a space between them, for readability and 
consistency with other instructions that have lists of register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:47:20 +00:00