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13594 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
b09701db9e Correctly handle <undef> tied uses when rewriting after a split. 
This fixes PR10463. A two-address instruction with an <undef> use
operand was incorrectly rewritten so the def and use no longer used the
same register, violating the tie constraint.

Fix this by always rewriting <undef> operands with the register a def
operand would use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-24 20:23:50 +00:00
Dan Gohman
4428069f10 Move the last uses of RetainFunc etc. over to using getRetainCallee() etc. 
so that a declaration for objc_retain is created when needed if it doesn't
already exist. rdar://9825114.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:29:21 +00:00
Jim Grosbach
6ab4e3dd23 Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:15:38 +00:00
Jim Grosbach
0e76edf8c0 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:13:00 +00:00
Jim Grosbach
bf2845c0d8 ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:06:05 +00:00
Jim Grosbach
6808f21757 ARM assembly parsing and encoding tests. 
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 21:34:56 +00:00
Bruno Cardoso Lopes
bb37dcd66f Fix test check! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135802 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:55:28 +00:00
Bruno Cardoso Lopes
dad38638e1 Fix PR10422 by adding the necessary AVX UCOMISD memory versions to 
load folding logic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:53:20 +00:00
Jim Grosbach
44a456332f ARM assembly parsing and encoding tests for SMLAWB/SMLAWT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:51:24 +00:00
Jim Grosbach
ce501030d9 ARM assembly parsing and encoding tests. 
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:30:40 +00:00
Jim Grosbach
b544f68b70 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:18:21 +00:00
Jim Grosbach
b206daaec1 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:11:20 +00:00
Jim Grosbach
0ffd4a09df ARM testcases for assembly parsing and encoding SMLA* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:01:34 +00:00
Rafael Espindola
23e31011fb Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64 
too. Patch by Jeff Muizelaar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135789 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:56:05 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:13:31 +00:00
Jim Grosbach
248e6c328c ARM encoding and assembly parsing tests. 
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:04:48 +00:00
Jim Grosbach
c27d4f9ea0 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:44:50 +00:00
Jim Grosbach
9076b6e8f4 ARM assembly parsing and encoding tests for SEL instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 16:59:33 +00:00
Bruno Cardoso Lopes
6683efb4cd -Inspected a AVX code block added by someone in early Feb. This was never used 
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes
08b076cc96 Although we already support this, add testcases for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135728 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:15:03 +00:00
Bruno Cardoso Lopes
74dad551d8 Add a DAGCombine for transforming 128->256 casts into a simple 
vxorps + vinsertf128 pair of instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 00:15:00 +00:00
Dan Gohman
856e13ddac Fix MergeInVectorType to check for vector types with the same alloc 
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:30:09 +00:00
Jim Grosbach
8409f04731 ARM parsing and encoding tests for SBC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:03:59 +00:00
Jim Grosbach
8ae45af794 ARM testcases for SADD/SASX parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:00:49 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:37:43 +00:00
Jim Grosbach
616fbdf987 ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:29:23 +00:00
Jim Grosbach
a4c34ab544 ARM parsing and encodings tests for saturating arithmetic insns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:18:28 +00:00
Jim Grosbach
10c7d70a4e ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:57:11 +00:00
Jim Grosbach
61b1b21e9a Add tests for ARM PKH assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:02:03 +00:00
Bruno Cardoso Lopes
dbd4fe2b0a - Register v16i16 as valid VR256 register class 
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
65b74e1d00 Add support for 256-bit versions of VPERMIL instruction. This is a new 
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 01:55:47 +00:00
Andrew Trick
c205a094bd LSR, correct fix for rdar://9786536. Silly casting bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 01:45:54 +00:00
Andrew Trick
c2c988e5e0 LSR must sometimes sign-extend before generating double constants. 
rdar://9786536


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 01:05:01 +00:00
Andrew Trick
37eb38d3f8 LSR crashes on an empty IVUsers list. 
rdar://9786536


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 00:40:04 +00:00
Devang Patel
4ec14b0dee While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 21:57:04 +00:00
Eli Friedman
73bfa4aecf Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 21:37:47 +00:00
Eli Friedman
a4d0bd84f7 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 19:36:11 +00:00
Jim Grosbach
88d1bc832c Add parsing/encoding tests for ARM ORR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:48:53 +00:00
Jim Grosbach
a678514459 Consolidate ARM NOP encoding test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:39:38 +00:00
Jim Grosbach
c3635c2e92 ARM parsing and encoding tests for MVN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:37:08 +00:00
Jim Grosbach
ab40f4b737 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:20:31 +00:00
Eli Friedman
0381c21d2d PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:14:33 +00:00
Evan Cheng
e76a33b956 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 05:58:47 +00:00
Andrew Trick
86c98145b2 indvars: Added getInsertPointForUses to find a valid place to truncate the IV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 05:32:06 +00:00
Eric Christopher
03c45f60f3 New pointer rotate test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 03:09:11 +00:00
Andrew Trick
9e92152f77 indvars test case for r135558. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 02:14:37 +00:00
Andrew Trick
f22d95749a indvars -disable-iv-rewrite fix: derived GEP IVs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 02:08:58 +00:00
Akira Hatanaka
db54826f20 Lower memory barriers to sync instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:30:50 +00:00
Evan Cheng
70955c2d12 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:14:32 +00:00