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15625 Commits

Author SHA1 Message Date
Eric Christopher
e24d66f525 Rework braindead conditionals I put in yesterday. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 22:07:27 +00:00
Eric Christopher
9f782d4dcf Fix thumb2 mode loads to have the correct operand ordering. Add a todo 
to fix this in the port.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 22:03:02 +00:00
Jim Grosbach
3197380143 Add ARM heuristic for when to allocate a virtual base register for stack 
access. rdar://8277890&7352504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 21:19:33 +00:00
Daniel Dunbar
fba88d49e3 MC/X86: Tweak imul recognition, previous hack only applies for the imul form 
taking immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:37:56 +00:00
Daniel Dunbar
ae528f65ba MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:24:18 +00:00
Daniel Dunbar
ee9102587e MC/X86: Warn on scale factors > 1 without index register, instead of erroring, 
for 'as' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:13:38 +00:00
Jim Grosbach
a273442891 Move enabling the local stack allocation pass into the target where it belongs. 
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:05:43 +00:00
Jim Grosbach
cd59dc5e81 add ARM cmd line option to force always using virtual base regs when possible. 
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 18:04:52 +00:00
Dan Gohman
92b651fb19 Fix X86's isLegalAddressingMode to recognize that static addresses 
need not be RIP-relative in small mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 15:55:12 +00:00
Kalle Raiskila
55aebef654 Fix SPU BE to use all the available return registers. 
llc used to assert on the added testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 11:50:48 +00:00
Kalle Raiskila
f53fdc2e45 Remove some dead code from SPU BE that remained 
from 64bit vector support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 11:05:51 +00:00
Bruno Cardoso Lopes
8878e21fe6 Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:16:15 +00:00
Bill Wendling
5e7044bd0e Add comments for what the condition code symbols mean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:11:30 +00:00
Eric Christopher
882d62e2db Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:10:52 +00:00
Eric Christopher
2012c7bb7b Fix the opcode and the operands for the load instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:10:04 +00:00
Eric Christopher
f06f309002 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 00:50:47 +00:00
Eric Christopher
cb0b04ba6f Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 00:07:24 +00:00
Eric Christopher
1dfb4d31e0 Don't need the extra register here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 23:28:04 +00:00
Eric Christopher
8654c71e56 Add some more "get address into register" code and a more TODOs/FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 23:14:31 +00:00
Eric Christopher
7fe55b739c Add an ARMFunctionInfo member and use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 22:32:45 +00:00
Eric Christopher
8300712c1e Start getting ARM loads/address computation going. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 21:44:12 +00:00
Bruno Cardoso Lopes
3efc0778c9 Start using target speficic nodes for shuffles: pshufhw and pshuflw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111837 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 20:41:02 +00:00
Gabor Greif
11bc1652c9 tyops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 20:30:51 +00:00
Chris Lattner
d80c7e1232 Add a new llvm.x86.int intrinsic, allowing access to the 
x86 int and int3 instructions.  Patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 19:39:25 +00:00
Chris Lattner
b7f243a638 random improvement for variable shift codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111813 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 17:30:29 +00:00
Anton Korobeynikov
4654a07e25 Revert invalid r111792. Jump tables are not broken on x86-64 / coff, 
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 07:38:51 +00:00
Michael J. Spencer
3464cec4d8 Workaround broken jump tables on x86-64 COFF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 04:45:37 +00:00
Anton Korobeynikov
699647cabc Use rip-rel addressing on win64 by default. For this we just 
defaults to small pic code model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111741 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 17:21:11 +00:00
Michael J. Spencer
da0bfcdaf9 MC: Add partial x86-64 support to COFF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111728 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 05:58:13 +00:00
Dan Gohman
8bef744518 Fix x86 fast-isel's cmp+branch folding to avoid folding when the 
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
bf8154a439 Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
3157ef1c13 This is the first step towards refactoring the x86 vector shuffle code. The 
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 22:55:05 +00:00
Bill Wendling
55ae515f9d Create the new linker type "linker_private_weak_def_auto". 
It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility.  The symbols are removed by the linker from the final linked image
(executable or dynamic library).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 22:05:50 +00:00
Bob Wilson
b31a11b466 Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and 
zero-extend operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 04:54:02 +00:00
Eric Christopher
f762fbe4fa Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 00:36:24 +00:00
Eric Christopher
cb59229a4a Add a couple of random comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 00:20:31 +00:00
Jim Grosbach
e2f556933e Better handling of offsets on frame index references. rdar://8277890 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 23:52:25 +00:00
Jim Grosbach
74d7b0af58 Add Thumb1 support for virtual frame indices. 
rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:52:13 +00:00
Eric Christopher
979e0a1414 Silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 15:35:27 +00:00
Chris Lattner
59f8a6a666 fix PR7465, mishandling of lcall and ljmp: intersegment long 
call and jumps.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 01:18:43 +00:00
Chris Lattner
efbdc8e236 minor progress towards fixing PR7465 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 01:00:34 +00:00
Eric Christopher
456144eb14 Add an AddOptionalDefs method and use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111489 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 00:37:05 +00:00
Bill Wendling
f0e132c385 Add the "isCompare" attribute to the defm instead of each individual instr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 00:05:48 +00:00
Jakob Stoklund Olesen
7552a3df39 Don't call Predicate_* in Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111468 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 23:56:46 +00:00
Eric Christopher
d96b02b3d6 Remove extra header. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 23:38:16 +00:00
Jim Grosbach
2b1e202e1c Enable ARM base register reuse to local stack slot allocation. Whenever a new 
frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111443 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 22:44:49 +00:00
Bill Wendling
ad422718f9 Minor simplification. Gets rid of a needless temporary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111430 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 21:32:07 +00:00
Bill Wendling
86b98b5874 Marked with ATTRIBUTE_USED so that clang doesn't complain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 18:40:57 +00:00
Jim Grosbach
74d803a58c Add hook for re-using virtual base registers for local stack slot access. 
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 17:57:37 +00:00
Kalle Raiskila
ca9460f5a0 Fix a bug with insertelement on SPU. 
The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 10:20:29 +00:00