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855 Commits

Author SHA1 Message Date
Chad Rosier
abd6674166 Fix a regression from r147481. 
Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 02:00:48 +00:00
Preston Gurd
e879cbae7c This patch adds instruction latencies for the SSE instructions 
to the instruction scheduler for the Intel Atom.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151590 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 23:35:03 +00:00
Pete Cooper
d18134f116 Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 03:51:49 +00:00
Jia Liu
44de83a7f6 some comment fix for X86 and ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:03:36 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
6e94e68b75 Remove the last of the old vector_shuffle patterns from X86 isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 07:02:34 +00:00
Craig Topper
233a64846e Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 08:14:53 +00:00
Craig Topper
7505626acd Still more vector_shuffle pattern removal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 07:23:41 +00:00
Craig Topper
4eaca023dc Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 05:48:49 +00:00
Craig Topper
3b17bf9a7c Recommit r150328. Previous test failures should be fixed by r150360. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 05:10:10 +00:00
NAKAMURA Takumi
7f42e9886e Revert r150328, "Remove more vector_shuffle patterns." 
It caused 3 failures on pre-penryn and non-x86(generic) hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 00:10:15 +00:00
Craig Topper
cc9231a05d Remove more vector_shuffle patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150328 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-12 08:14:35 +00:00
Craig Topper
26f927951b Remove more vector_shuffle patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150321 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-12 01:07:34 +00:00
Craig Topper
1f2fa99b2a Remove more vector_shuffle patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150314 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 23:31:01 +00:00
Craig Topper
a819c397e7 Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 07:43:35 +00:00
Craig Topper
bc0e4bf754 Remove a couple unneeded intrinsic patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150067 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 08:29:30 +00:00
Craig Topper
5a313bb7e8 Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 06:36:57 +00:00
Craig Topper
dbd98a4b1b Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 06:28:42 +00:00
Craig Topper
5b209e84f4 Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 03:14:49 +00:00
Elena Demikhovsky
dcabc7bca9 Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:10:43 +00:00
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 23:20:51 +00:00
Craig Topper
cc30006391 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 07:50:31 +00:00
Craig Topper
3982b3cc7b Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-27 07:09:40 +00:00
Victor Umansky
668f7ac9e4 Fix for the following bug in AVX codegen for double-to-int conversions: 
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149056 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 08:51:39 +00:00
Craig Topper
15388c4666 Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 07:31:30 +00:00
Craig Topper
e566cd0f4d Remove some more patterns by custom lowering intrinsics to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 07:18:03 +00:00
Craig Topper
969ba287cd Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 06:43:11 +00:00
Craig Topper
4bb3f34b22 Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 05:37:32 +00:00
Craig Topper
bce73e0a8c Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 04:42:03 +00:00
Craig Topper
042883f5da Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 03:52:09 +00:00
Craig Topper
7925e2555d Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148687 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 08:18:28 +00:00
Craig Topper
80e46360e9 Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148684 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 06:16:53 +00:00
Craig Topper
2b21fbaf11 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148672 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 00:06:44 +00:00
Craig Topper
1906d32e55 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 23:36:02 +00:00
Craig Topper
67609fd0eb Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 22:42:16 +00:00
Craig Topper
ed2e13d667 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 19:15:14 +00:00
Craig Topper
6fdf3d54d2 Move some vector shift patterns into their instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148643 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 00:41:20 +00:00
Craig Topper
babb1459f3 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148641 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-21 18:37:15 +00:00
Craig Topper
0e2037ba2b Add support for selecting 256-bit PALIGNR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 05:53:00 +00:00
Craig Topper
b7ab7fe053 Give priority to AVX over SSE for 128-bit floating point unpck instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148233 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-16 09:56:42 +00:00
Craig Topper
d07ef50ca1 Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 18:29:57 +00:00
Chad Rosier
d32d3b758f Fix pasto from r146196. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148167 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-14 01:50:21 +00:00
Craig Topper
0518970dc8 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148112 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 09:21:41 +00:00
Craig Topper
12216172c0 Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 08:12:35 +00:00
Craig Topper
c30432ab57 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-13 06:59:47 +00:00
Chad Rosier
1b2983bb23 Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a few 
failing test cases on our internal AVX nightly tester.
rdar://10663637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 22:14:06 +00:00
Craig Topper
c6d59954d8 Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-10 06:30:56 +00:00
Craig Topper
8ffc964582 Add HasAVX predicate to some of the AVX patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147769 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 08:34:00 +00:00
Craig Topper
47cf1003fa Reorder a bunch of patterns to put the AVX version first thus giving it priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147768 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 08:10:38 +00:00
Craig Topper
5feb5dae93 Clean up patterns for MOVNT*. Not sure why there were floating point types on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147767 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-09 06:52:46 +00:00