Nadav Rotem
e503319874
LoopVectorizer:
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1. Add code to estimate register pressure.
2. Add code to select the unroll factor based on register pressure.
3. Add bits to TargetTransformInfo to provide the number of registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-04 17:48:25 +00:00
Nadav Rotem
e12bf18754
Revert revision: 171467. This transformation is incorrect and makes some tests fail. Original message:
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Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1.
Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-04 17:35:21 +00:00
Elena Demikhovsky
ab70320908
Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1.
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Added a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-03 08:48:33 +00:00
Michael Gottesman
e33a8b8c2f
Revert "Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks."
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This reverts commit r171461 since it breaks the following tests:
Clang :: Analysis/outofbound-notwork.c
Clang :: Analysis/string-fail.c
Clang :: CXX/basic/basic.lookup/basic.lookup.qual/p6-0x.cpp
Clang :: CXX/basic/basic.lookup/basic.lookup.unqual/p15.cpp
Clang :: CXX/dcl.dcl/dcl.spec/dcl.fct.spec/p4.cpp
Clang :: CXX/dcl.dcl/dcl.spec/dcl.stc/p10.cpp
Clang :: CXX/temp/temp.param/p14.cpp
Clang :: CXX/temp/temp.res/temp.dep.res/temp.point/p1.cpp
Clang :: CodeGen/2009-02-13-zerosize-union-field-ppc.c
Clang :: CodeGen/blocks-2.c
Clang :: CodeGen/libcalls-d.c
Clang :: CodeGen/libcalls-ld.c
Clang :: CodeGenCXX/conversion-function.cpp
Clang :: CodeGenCXX/debug-info-limit-type.cpp
Clang :: CodeGenCXX/inheriting-constructor.cpp
Clang :: FixIt/fixit-errors.c
Clang :: FixIt/fixit-pmem.cpp
Clang :: Modules/namespaces.cpp
Clang :: PCH/changed-files.c
Clang :: PCH/pr4489.c
Clang :: PCH/source-manager-stack.c
Clang :: Parser/cxx-ambig-decl-expr-xfail.cpp
Clang :: SemaCXX/switch-implicit-fallthrough-cxx98.cpp
Clang :: SemaTemplate/instantiate-function-1.mm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171466 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-03 08:18:30 +00:00
Craig Topper
56bc0ab095
Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171461 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-03 06:40:20 +00:00
Hal Finkel
82860f63e1
Add a subtype parameter to VTTI::getShuffleCost
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In order to cost subvector insertion and extraction, we need to know
the type of the subvector being extracted.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171453 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-03 02:34:09 +00:00
Kevin Enderby
5bf3a28b36
Adds missing aliases for fcom and fcomp instructions without arguments.
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Patch by Michael M Kuperstein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 21:20:15 +00:00
Nadav Rotem
e3b2489f4f
AVX: Fix a bug in WidenMaskArithmetic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 17:41:03 +00:00
Chandler Carruth
0b8c9a80f2
Move all of the header files which are involved in modelling the LLVM IR
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into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
Chandler Carruth
58a2cbef4a
Resort the #include lines in include/... and lib/... with the
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utils/sort_includes.py script.
Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 10:22:59 +00:00
Craig Topper
3af9323228
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 08:00:39 +00:00
Craig Topper
3cca7df7c7
Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 07:27:49 +00:00
Rafael Espindola
9478673ce0
Revert 171351. It broke MC/X86/x86-32-avx.s.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 01:35:11 +00:00
Craig Topper
b511048cd0
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 20:53:20 +00:00
Craig Topper
117e4d2e19
Remove unused argument from a multiclass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171340 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 03:42:44 +00:00
Craig Topper
76f94fd361
Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 03:30:21 +00:00
Craig Topper
42ab0d75ab
Remove 2 unused multiclasses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 02:02:45 +00:00
Craig Topper
5284f97632
Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 00:11:07 +00:00
Craig Topper
dd9ccdb050
Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-31 23:49:05 +00:00
Bill Wendling
9d30e7208e
Remove the getAttributesAtIndex and getNumAttrs methods in favor of using the getAttrSomewhere predicate. This prevents the uses of 'Attribute' as a collection of attributes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-31 00:49:59 +00:00
Nuno Lopes
98281a2050
convert a bunch of callers from DataLayout::getIndexedOffset() to GEP::accumulateConstantOffset().
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The later API is nicer than the former, and is correct regarding wrap-around offsets (if anyone cares).
There are a few more places left with duplicated code, which I'll remove soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 16:25:48 +00:00
Bill Wendling
94e94b3506
Use the predicate methods off of AttributeSet instead of Attribute.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 13:50:49 +00:00
Bill Wendling
8b62abdd7b
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 13:01:51 +00:00
Bill Wendling
39cd0c8e47
Remove Function::getParamAttributes and use the AttributeSet accessor methods instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 12:45:13 +00:00
Bill Wendling
831737d329
Remove the Function::getFnAttributes method in favor of using the AttributeSet
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directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 10:32:01 +00:00
Bill Wendling
377660355c
s/hasAttribute/contains/g to be more consistent with other method names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 09:17:46 +00:00
Craig Topper
22d8f0d685
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 18:18:20 +00:00
Craig Topper
6f57f39e4a
Merge similar functionality using a nested switch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171229 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 17:19:06 +00:00
Craig Topper
6d183e4007
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 16:44:25 +00:00
Jakub Staszak
c20323a758
Simplify code, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 15:57:26 +00:00
Jakub Staszak
3c0307d760
Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 15:23:06 +00:00
Nadav Rotem
ae34b4280e
CostModel: initial checkin for code that estimates the cost of special shuffles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-28 08:19:03 +00:00
Nadav Rotem
40ef8b7548
wrap 80-col lines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-28 07:28:43 +00:00
Nadav Rotem
0509db2738
AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-28 05:45:24 +00:00
Nadav Rotem
587fb1dd30
Reverse the 'if' condition and reduce the indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 23:08:05 +00:00
Craig Topper
cccccabd07
Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 22:53:47 +00:00
Nadav Rotem
1a330af3b5
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 22:47:16 +00:00
Craig Topper
d5fc507ff1
Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 18:51:50 +00:00
Nadav Rotem
d6fb53adb1
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
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register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 08:15:45 +00:00
Nadav Rotem
3c22a44400
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
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The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 07:45:10 +00:00
Craig Topper
068aec586d
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 07:16:08 +00:00
Craig Topper
d0f28c0958
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 06:34:54 +00:00
Craig Topper
87073aad8f
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 03:35:44 +00:00
Craig Topper
766cbae4b1
Mark the divide instructions as hasSideEffects=0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 03:01:18 +00:00
Craig Topper
0b9c5e268f
Add hasSideEffects=0 to CMP*rr_REV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 02:08:46 +00:00
Craig Topper
5e6a86c7f0
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 02:01:33 +00:00
Craig Topper
e9fd6ad567
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 23:27:57 +00:00
Craig Topper
ee5b63cb52
Add hasSideEffects=0 to some atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 23:08:12 +00:00
Craig Topper
b87a5b3a1f
Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 22:19:23 +00:00
Craig Topper
37cb8398c8
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 21:30:22 +00:00