Evan Cheng
8e59ea998f
Spill / restore should avoid modifying the condition register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-07 00:06:56 +00:00
Evan Cheng
ad1b9a503c
Copy and paste bug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33658 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-30 08:22:33 +00:00
Evan Cheng
c322a9ac14
Misseed thumb jumptable branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33656 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-30 08:03:06 +00:00
Evan Cheng
29836c330f
Factor GetInstSize() out of constpool island pass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-29 23:45:17 +00:00
Jim Laskey
1ee2925742
Make LABEL a builtin opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-26 14:34:52 +00:00
Evan Cheng
a8e2989ece
ARM backend contribution from Apple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19 07:51:42 +00:00
Evan Cheng
c0f64ffab9
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-27 23:37:22 +00:00
Rafael Espindola
3d7d39ab15
fix warning about missing newline at end of file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31162 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-24 17:07:11 +00:00
Chris Lattner
578e64a041
implement uncond branch insertion, mark branches with isBranch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31160 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-24 16:47:57 +00:00
Rafael Espindola
3ad5e5cf99
add shifts to addressing mode 1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-13 12:09:43 +00:00
Rafael Espindola
7cca7c5317
partial implementation of the ARM Addressing Mode 1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-11 17:25:40 +00:00
Rafael Espindola
46adf8119d
change the addressing mode of the str instruction to reg+imm
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-08 20:35:03 +00:00
Rafael Espindola
aefe14299a
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-10 01:41:35 +00:00
Rafael Espindola
49e4415587
handle the "mov reg1, reg2" case in isMoveInstr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27 21:52:45 +00:00
Rafael Espindola
4b442b528a
implement minimal versions of
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ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28431 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-23 02:48:20 +00:00
Rafael Espindola
7bc59bc395
added a skeleton of the ARM backend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
