Duraid Madina
f55e403ef9
codegen immediate forms of add/sub/shift
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21130 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-07 12:33:38 +00:00
Duraid Madina
18c0c6bcc4
add immediate forms of add, sub, shift
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21129 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-07 12:32:24 +00:00
Nate Begeman
7ddecb4186
Pattern match bitfield insert, which helps shift long by immediate, among
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other things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21127 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 23:51:40 +00:00
Nate Begeman
020ef42c19
Fix some shift bugs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21126 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 22:42:08 +00:00
Alkis Evlogimenos
aeca558788
Make these 64 bit constants so that this compiles on x86-32 as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21125 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 22:09:40 +00:00
Andrew Lenharth
a565c275b5
added sdiv by 2^k and works for neg divisors also
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21124 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 22:03:13 +00:00
Andrew Lenharth
f77f395043
fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21121 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 20:59:59 +00:00
Chris Lattner
6d027f2e6f
Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not
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properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21120 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 20:59:35 +00:00
Andrew Lenharth
4b8ac1559a
Added Nate's div by constant stuff, also scaled operations!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21116 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 20:25:34 +00:00
Chris Lattner
ce91ec9ae6
Fix a namespace issue, reported by Vladimir Merzliakov!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21115 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 19:45:39 +00:00
Duraid Madina
4826a0786d
steal sampo's div-by-constant-power-of-2 stuff
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thanks sampo!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21113 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 09:55:17 +00:00
Duraid Madina
b366a02ff2
add fms instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21112 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 09:54:09 +00:00
Nate Begeman
27b4c23b80
Fixed version of optimized integer divide is now fixed. Calculate the
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quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21111 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 06:44:57 +00:00
Duraid Madina
b70c2f3ef7
lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
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care of this ourselves
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21110 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 06:18:36 +00:00
Duraid Madina
4ee131ffa8
make sure 'special' registers don't get allocated
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21109 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 06:17:54 +00:00
Chris Lattner
8db0af1c8d
Add (untested) support for MULHS and MULHU.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21107 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 04:21:07 +00:00
Chris Lattner
1e6a71524e
add signed versions of the extra precision multiplies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21106 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 04:19:22 +00:00
Nate Begeman
8f52980f03
Turn off the div -> mul optimization until it works correctly 100% of the
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time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21105 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 03:36:33 +00:00
Nate Begeman
815d6dac1e
Add support for MULHS and MULHU nodes
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Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 00:25:27 +00:00
Andrew Lenharth
2513ddc239
added lowerargs support for varargs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21101 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 20:51:46 +00:00
Nate Begeman
ad5f65c74b
Behold, rlwinm with certain immediate arguments is printed as the much more
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readable slwi or srwi (shift left/right word immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21099 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 18:19:50 +00:00
Nate Begeman
a3829d5580
Fix cut & paste errors (32->64), and codegen float->int more optimally.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21098 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 17:32:30 +00:00
Tanya Lattner
ac6e2dbf52
Updated to use dep analyzer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21097 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 16:36:44 +00:00
Nate Begeman
d3e6b94020
Remove 64 bit simple ISel, it never worked correctly
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Add initial (buggy) implementation of 64 bit pattern ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 08:51:15 +00:00
Nate Begeman
c8c5c8f0fa
Back out the previous change to SelectBranchCC, since there are cases it
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could miscompile. A correct solution will be found in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21095 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 04:32:16 +00:00
Nate Begeman
439b444cad
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
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indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21094 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 04:22:58 +00:00
Nate Begeman
80196b1331
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21091 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 00:15:08 +00:00
Nate Begeman
93075ec0a5
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21090 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 23:40:36 +00:00
Nate Begeman
178bb34ee5
Add support for multiply-add, multiply-sub, and their negated versions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 23:01:51 +00:00
Nate Begeman
d860aa62ac
Make sure that arg regs used by the call instruction are marked as such, so
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that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21086 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 22:17:48 +00:00
Nate Begeman
04ec80173b
Remove unnecessary register copy now that regalloc is fixed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21085 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 21:48:13 +00:00
Nate Begeman
c3e2db407e
i1 loads should also be from the low byte of the argument word.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21077 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 09:09:00 +00:00
Nate Begeman
e584668f04
Fix i64 return, fix CopyFromReg
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 06:52:38 +00:00
Duraid Madina
6e02e6842a
fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is
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an ugly hack, but it seems to work. I should fix this properly and add a test
as well.
fixes multisource/obsequi (maybe others)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21075 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 05:05:52 +00:00
Duraid Madina
09c61b9c19
add implicit use op
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21074 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 04:50:57 +00:00
Nate Begeman
6644d4c933
Full varargs support. All of UnitTests now passes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21070 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 23:11:17 +00:00
Nate Begeman
4ec0cbdf15
Pass the correct value for the chain to the store
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21066 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 22:22:56 +00:00
Nate Begeman
fa55470e39
Fix SHL_PARTS
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Start implementation of integer varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21065 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 22:13:27 +00:00
Andrew Lenharth
63b720ac7c
is this simpler? I think it is simpler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21064 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 20:35:21 +00:00
Andrew Lenharth
500d025bd9
fix 101 regressions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21063 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 18:24:50 +00:00
Duraid Madina
162a837f63
.bss is no problem here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21061 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 14:52:01 +00:00
Nate Begeman
aa73a9f16f
Keeping up with the Joneses.
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Implement not, nor, nand, and eqv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21060 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 11:20:20 +00:00
Andrew Lenharth
10c085b525
Select optimization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21051 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 22:32:39 +00:00
Andrew Lenharth
0eaf6ce2ef
Try several things. 1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21046 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 21:06:51 +00:00
Andrew Lenharth
7332f3e05d
FNEG/FABS/UNDEF
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21029 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 19:11:07 +00:00
Andrew Lenharth
30b46d41bc
FNEG/FABS
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21028 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 19:04:58 +00:00
Duraid Madina
32c46f33b7
ia64 asmprinter fixes:
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- turn off assembler's autoalignment
- set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
functions have their value wrapped in @fptr(), so that a function
descriptor will be materialized for that function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21025 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 12:30:47 +00:00
Duraid Madina
75c9fcbdcc
support IDEF, fnegabs (thanks sampo)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21023 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 10:33:53 +00:00
Duraid Madina
5c156b7473
add fnegabs op
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21022 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 10:06:27 +00:00
Nate Begeman
27eeb00a1a
Set shift amount to Extend
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Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 05:59:34 +00:00