Commit Graph

70715 Commits

Author SHA1 Message Date
Che-Liang Chiou
f78847ee7b ptx: add set.p instruction and related changes to predicate execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 11:26:01 +00:00
Mikhail Glushenkov
046d0bdaf0 Emacs mode string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 04:20:57 +00:00
Francois Pichet
606957fdd6 Correct small comment order typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 02:30:32 +00:00
Jin-Gu Kang
948d9e7ec7 This case is solved by Scalar Replacement of Aggregates (DT) and
Early CSE pass so this patch reverts it to original source code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 01:21:00 +00:00
Che-Liang Chiou
c2ec0f974d ptx: add basic support of predicate execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-13 17:26:00 +00:00
Jin-Gu Kang
198e97c423 Add comment as following:
load and store reference same memory location, the memory location
is represented by getelementptr with two uses (load and store) and
the getelementptr's base is alloca with single use. At this point,
instructions from alloca to store can be removed.
(this pattern is generated when bitfield is accessed.)
For example,
%u = alloca %struct.test, align 4               ; [#uses=1]
%0 = getelementptr inbounds %struct.test* %u, i32 0, i32 0;[#uses=2]
%1 = load i8* %0, align 4                       ; [#uses=1]
%2 = and i8 %1, -16                             ; [#uses=1]
%3 = or i8 %2, 5                                ; [#uses=1]
store i8 %3, i8* %0, align 4


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-13 14:05:51 +00:00
Oscar Fuentes
98f6ddc3c5 LTO is not ready for Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-13 03:06:59 +00:00
Jakob Stoklund Olesen
5522e8a936 Now that we are deleting unused live intervals during allocation, pointers may be reused.
Use the virtual register number as a cache tag instead. They are not reused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-13 01:29:32 +00:00
Jakob Stoklund Olesen
7792e980c4 Tell the register allocator about new unused virtual registers.
This allows the allocator to free any resources used by the virtual register,
including physical register assignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-13 01:23:11 +00:00
Oscar Fuentes
b56130f96b Build EnhancedDisassembly as a shared library too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 22:01:47 +00:00
Oscar Fuentes
255d0253df Build CompilerDriver library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127554 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 22:01:42 +00:00
Oscar Fuentes
8e3db304c1 Build LTO as a static library too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 22:01:36 +00:00
Oscar Fuentes
54efb7371a Build LTO as a static library too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 17:32:30 +00:00
Benjamin Kramer
14b2a59301 Teach ComputeMaskedBits about sub nsw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 17:18:11 +00:00
Oscar Fuentes
879d3a98a2 Whe we build a shared library, add its list of used libraries to the
link command.

Fixed a pair of IF expressions too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 16:48:54 +00:00
Oscar Fuentes
798403babd Update link components for llvm-dis and LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 16:48:49 +00:00
Duncan Sands
ba9934648f Speculatively revert commit 127478 (jsjodin) in an attempt to fix the
llvm-gcc-i386-linux-selfhost and llvm-x86_64-linux-checks buildbots.
The original log entry:
Remove optimization emitting a reference insted of label difference, since
it can create more relocations. Removed isBaseAddressKnownZero method,
because it is no longer used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127540 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 13:07:37 +00:00
Jin-Gu Kang
c5c03f9024 This patch removes some of useless instructions generated by bitfield access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 12:18:44 +00:00
Jakob Stoklund Olesen
b1adbd1f67 Include snippets in the live stack interval.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127530 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 04:25:36 +00:00
Jakob Stoklund Olesen
10a433238f Spill multiple registers at once.
Live range splitting can create a number of small live ranges containing only a
single real use. Spill these small live ranges along with the large range they
are connected to with copies. This enables memory operand folding and maximizes
the spill to fill distance.

Work in progress with known bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 04:17:20 +00:00
Sean Callanan
7a387e4d9d Fixed the comparison operator for the enhanced
disassembler's disassembler map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 03:27:54 +00:00
Jakob Stoklund Olesen
55768d763d That's it, I am declaring this a failure of the C++03 STL.
There are too many compatibility problems with using mixed types in
std::upper_bound, and I don't want to spend 110 lines of boilerplate setting up
a call to a 10-line function. Binary search is not /that/ hard to implement
correctly.

I tried terminating the binary search with a linear search, but that actually
made the algorithm slower against my expectation. Most live intervals have less
than 4 segments. The early test against endIndex() does pay, and this version is
25% faster than plain std::upper_bound().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:50:35 +00:00
Eric Christopher
8b3000b08e Saving files before committing is overrated.
Add a RUN line to this test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:36:23 +00:00
Eric Christopher
af3dce5149 Sometimes isPredicable lies to us and tells us we don't need the operands.
Go ahead and add them on when we might want to use them and let
later passes remove them.

Fixes rdar://9118569


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:09:29 +00:00
Jim Grosbach
7d3a16a6f8 Remove no-longer-correct special case for disasm of ARM BL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:05:29 +00:00
Jim Grosbach
34e98e968f Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 00:51:00 +00:00
Jim Grosbach
f859a545de Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 00:45:26 +00:00
Jim Grosbach
cea5afc985 Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:25:21 +00:00
Jim Grosbach
72422d38ba Pseudo-ize the ARM 'B' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:24:15 +00:00
Jim Grosbach
3c5edaaf59 Remove dead code. These ARM instruction definitions no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:15:02 +00:00
Jim Grosbach
5380bbf606 Remove dead code. These ARM instruction definitions no longer exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:11:41 +00:00
Jim Grosbach
f219f3135d Pseudo-ize VMOVDcc and VMOVScc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:09:50 +00:00
Jim Grosbach
b181ad3486 80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 23:00:16 +00:00
Jim Grosbach
dd11988c99 Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
effect that we get proper instruction printing using the "pop" mnemonic for it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 22:51:41 +00:00
Cameron Zwarich
899eaa3569 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:52:04 +00:00
Cameron Zwarich
53aac15a60 Fix the GCC test suite issue exposed by r127477, which was caused by stack
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:51:56 +00:00
Owen Anderson
2ce5bf188d Teach FastISel to support register-immediate-immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127496 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:33:55 +00:00
Jim Grosbach
2a09f878ef 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:02:27 +00:00
Jim Grosbach
108e4dbecb Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:59:19 +00:00
Jim Grosbach
b9cf5f8763 Remove dead code. These ARM instruction definitions don't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:51:07 +00:00
Jim Grosbach
958108ad14 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
as for VDUP32d and VDUP32q, respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:44:08 +00:00
Jim Grosbach
81bb6551e6 Remove dead code. These ARM instruction definitions don't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:38:18 +00:00
Jim Grosbach
8b8515c225 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:31:17 +00:00
Jim Grosbach
1558df79b4 ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:18:05 +00:00
Jim Grosbach
f0112a224f This FIXME has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 20:07:37 +00:00
Jim Grosbach
e672ff8430 Properly pseudo-ize ARM MVNCCi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127482 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:55:55 +00:00
Jim Grosbach
6a44adade2 Add missing 'return on failure'. Previously we'd crash after emitting
the diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:52:52 +00:00
Jan Sjödin
e4f6d7461a Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:37:02 +00:00
Daniel Dunbar
950d3db5f4 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:30:30 +00:00
Oscar Fuentes
4839ded3bd Force re-linking of LLVMgold.so when its exports file changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 18:27:13 +00:00