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2639 Commits

Author SHA1 Message Date
Chris Lattner
93677c99a4 remove unwind info, add test for asmprinting of jump table labels with (%rip) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74337 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:16:49 +00:00
Evan Cheng
2c2fb823b9 Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74336 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:00:19 +00:00
David Goodwin
24062ac5be Thumb-2 has CLZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74322 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 20:47:43 +00:00
David Goodwin
7ce720b448 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 20:45:56 +00:00
Daniel Dunbar
d2deed0091 More spelling Count as count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74306 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:35:07 +00:00
Daniel Dunbar
039c43dccc Spell Count as count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74298 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:21:54 +00:00
David Goodwin
2634e98a93 Add Thumb-2 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74295 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:10:30 +00:00
David Goodwin
93d95bd2c3 ADC used to implement adde should use "adcs" opcode instead of "adc". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74293 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 18:07:25 +00:00
David Goodwin
caffbd7b01 ORN and BIC tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74289 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 16:20:06 +00:00
David Goodwin
83b3593478 Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. 
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74288 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 16:10:07 +00:00
Evan Cheng
6677f51127 Fix tests: Count -> count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74282 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 07:05:57 +00:00
Evan Cheng
c0ad80fd9e Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74276 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 05:59:16 +00:00
Daniel Dunbar
12cccf10a7 Fix spelling of 'count' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 01:33:02 +00:00
Evan Cheng
6267422318 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 23:34:10 +00:00
David Goodwin
0919a916bf Use MVN for ~t2_so_imm immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74223 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 23:11:21 +00:00
Bill Wendling
06b76b834f Don't grep the -debug output. This isn't the way to test changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74211 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 21:59:32 +00:00
Chris Lattner
5f04d1e522 down with unwind info :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 21:48:17 +00:00
Evan Cheng
1e249e3705 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-25 20:59:23 +00:00
Evan Cheng
a09b9ca10f Add Thumb2 pc relative add. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 23:47:58 +00:00
Evan Cheng
2e1af3529b We should run these tests as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74121 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 21:36:26 +00:00
Chris Lattner
7556bfd6af unwind info not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74112 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 19:48:04 +00:00
Evan Cheng
9f76ed5127 Move thumb and thumb2 tests into separate directories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74068 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 06:36:07 +00:00
Evan Cheng
ef5d070bbe Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74053 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 02:05:51 +00:00
Dan Gohman
40a5a1b39e Extend ScalarEvolution's multiple-exit support to compute exact 
trip counts in more cases.

Generalize ScalarEvolution's isLoopGuardedByCond code to recognize
And and Or conditions, splitting the code out into an
isNecessaryCond helper function so that it can evaluate Ands and Ors
recursively, and make SCEVExpander be much more aggressive about
hoisting instructions out of loops.

test/CodeGen/X86/pr3495.ll has an additional instruction now, but
it appears to be due to an arbitrary register allocation difference.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-24 01:18:18 +00:00
Evan Cheng
a67efd1226 Proper patterns for thumb2 shift and rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 19:39:13 +00:00
Bob Wilson
5bafff36c7 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 23:27:02 +00:00
Evan Cheng
524961e57f It's coalescer, not coaleser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:09:17 +00:00
Bob Wilson
54fc124d72 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 21:01:46 +00:00
Evan Cheng
81909b7423 Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 20:49:32 +00:00
Evan Cheng
8dcbbdd00e hasFP should return true if frame address is taken. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 18:38:48 +00:00
Rafael Espindola
1c3329f707 Fix PR4185. 
Handle FpSET_ST0_80 being used when ST0 is still alive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-21 12:02:51 +00:00
Chris Lattner
5c0b16d0c4 change TLS_ADDR lowering to lower to a real mem operand, instead of matching as 
a global with that gets printed with the :mem modifier.  All operands to lea's 
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this.  There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).

This also makes the use of EBX explicit in the operand list in the 32-bit, 
instead of implicit in the instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73834 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 20:38:48 +00:00
Chris Lattner
6bfb669f82 no need for unwind info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73832 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 19:48:26 +00:00
Chris Lattner
811ac0b088 no need for unwind info here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 19:43:09 +00:00
Evan Cheng
694f6c81e8 Fix PR4419: handle defs of partial uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73816 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-20 04:34:51 +00:00
Dan Gohman
2781f30eac Re-apply r73718, now that the fix in r73787 is in, and add a 
hand-crafted testcase which demonstrates the bug that was exposed
in 254.gap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73793 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 23:23:27 +00:00
Evan Cheng
ae69a2a12b Enable arm pre-allocation load / store multiple optimization pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 23:17:27 +00:00
Evan Cheng
73a76736fb Revert 73718. It's breaking 254.gap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73783 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 21:15:06 +00:00
Eli Friedman
7e2242be71 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to 
handle with an SSE2 instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73760 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 07:00:55 +00:00
Eli Friedman
6b7bb42c36 Mark a few Thumb instructions commutable; just happened to spot this 
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-19 01:43:08 +00:00
Evan Cheng
b13bafe5c1 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73720 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 20:37:15 +00:00
Dan Gohman
4658c9b4ea Generalize LSR's OptimizeSMax to handle unsigned max tests as well 
as signed max tests. Along with r73717, this helps CodeGen avoid
emitting code for a maximum operation for this class of loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73718 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 20:23:18 +00:00
Dan Gohman
4e8a98519e Remove the code from IVUsers that attempted to handle 
casted induction variables in cases where the cast
isn't foldable. It ended up being a pessimization in
many cases. This could be fixed, but it would require
a bunch of complicated code in IVUsers' clients. The
advantages of this approach aren't visible enough to
justify it at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73706 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-18 16:54:06 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
a4e968cb0e Make the test target-neutral 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73547 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 20:25:25 +00:00
Anton Korobeynikov
2932795309 GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 18:49:08 +00:00
Evan Cheng
67fcf56ac4 If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. 
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 07:12:58 +00:00
Eli Friedman
db3c169f3a Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 
support for x86, and UMULO/SMULO for many architectures, including PPC 
(PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's
not bad.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73477 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-16 06:58:29 +00:00
Dan Gohman
9a8c5807f8 Update this test to use fmul instead of mul. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73436 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 22:49:34 +00:00
Evan Cheng
2077e18caf ifcvt should ignore cfg where true and false successors are the same. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73423 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-15 21:24:34 +00:00