Commit Graph

92281 Commits

Author SHA1 Message Date
Hal Finkel
fc32605ff3 Expose InsertPreheaderForLoop from LoopSimplify to other passes
Other passes, PPC counter-loop formation for example, also need to add loop
preheaders outside of the regular loop simplification pass. This makes
InsertPreheaderForLoop a global function so that it can be used by other
passes.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:47:07 +00:00
Justin Holewinski
9b39c726a0 [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182298 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:42:18 +00:00
Justin Holewinski
d223675593 [NVPTX] Add programmatic interface to NVVMReflect pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:42:16 +00:00
Hal Finkel
85c08b059c Rename PPC MTCTRse to MTCTRloop
As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182296 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:08:37 +00:00
Hal Finkel
e50c8c1f81 Add a PPCCTRLoops verification pass
When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.

In short, this is to help us sleep better at night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182295 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 16:08:17 +00:00
Benjamin Kramer
d54bf7ceef R600: Fix bug detected by GCC warning.
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:58:43 +00:00
Tom Stellard
4f8d90df45 R600: Fix rotr.ll on non-asserts builds
The -debug-only option is only available on asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182291 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:28:48 +00:00
Tom Stellard
5ad6d082fc R600/SI: Use a multiclass for MUBUF_Load_Helper
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:31 +00:00
Tom Stellard
307a84425c R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:28 +00:00
Tom Stellard
0bbfc9313c R600/SI: Add pattern for rotr
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:24 +00:00
Tom Stellard
ba534c2143 R600: Swap the legality of rotl and rotr
The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:19 +00:00
Tom Stellard
a9d5d0b346 R600/SI: Add patterns for 64-bit shift operations
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:12 +00:00
Tom Stellard
fbdd318120 R600/SI: Use the same names for VOP3 operands and encoding fields
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:08 +00:00
Tom Stellard
9bf4590aaa R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:01 +00:00
Mihai Popa
30a7a7c1fd VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:57:05 +00:00
Mihai Popa
bac932e9c3 Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:42:43 +00:00
Richard Sandiford
44b486ed78 [SystemZ] Add long branch pass
Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 14:23:08 +00:00
Benjamin Kramer
e932e891e5 Enable pod-like optimizations for pred and succ iterators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 13:12:58 +00:00
Justin Holewinski
7536ecf291 [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.

The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space.  Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 12:13:32 +00:00
Justin Holewinski
55fdf53629 [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 12:13:28 +00:00
Stepan Dyatkovskiy
083bc97344 PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:

Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack  ------ ...

FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.

We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.

This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 08:01:34 +00:00
Renato Golin
3a408fa878 Disable remote MCJIT on pre-v6 ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 07:46:06 +00:00
Bob Wilson
a4de3f2c85 Partially revert change in r181200 that tried to simplify JIT unit test #ifdefs.
The export list for this test requires the following symbols to be available:
  JITTest_AvailableExternallyFunction
  JITTest_AvailableExternallyGlobal
The change in r181200 commented them out, which caused the test to fail to
link, at least on Darwin. I have only reverted the change for arm, since I
can't test the other targets and since it sounds like that change was fixing
real problems for those other targets. It should be possible to rearrange the
code to keep those definitions outside the #ifdefs, but that should be done by
someone who can reproduce the problems that r181200 was trying to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 06:13:09 +00:00
Jakob Stoklund Olesen
89f530ebbf Also expand 64-bit bitcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
5e5b78ca36 Implement spill and fill of I64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
900622e099 Mark i64 SETCC as expand so it is turned into a SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 00:28:36 +00:00
Benjamin Kramer
4dc8bdf87d Replace some bit operations with simpler ones. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 22:01:57 +00:00
Jakob Stoklund Olesen
634123e98d Don't use %g0 to materialize 0 directly.
The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
60abcb786e Select i64 values with %icc conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:38:21 +00:00
Bob Wilson
2ed2ad00f9 Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>
This fixes a bootstrapping problem with builds for Apple ARM targets.
Clang had the wrong prototype for __clear_cache with ARM targets.  Rafael
fixed that in clang svn r181784 and r181810, but without those changes,
we can't build this code for ARM because clang reports an error about the
declaration in Memory.inc not matching the builtin declaration. Some of our
buildbots need to use an older compiler that doesn't have the clang fix.
Since __clear_cache is never used here when __APPLE__ is defined, I'm just
conditionalizing the declaration to match that. I also moved the declaration
of sys_icache_invalidate inside the conditional for __APPLE__ while I was at
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:33:51 +00:00
Jakob Stoklund Olesen
51d46c36bc Add floating point selects on %xcc predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:33:11 +00:00
Jakob Stoklund Olesen
89db6732fb Implement SPselectfcc for i64 operands.
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:20:54 +00:00
Renato Golin
4e4464bf74 SubArch support in MCJIT unittest
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:10:10 +00:00
Venkatraman Govindaraju
21886a495a [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.
Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 20:07:20 +00:00
Tim Northover
233a4d7124 AArch64: enable MCJIT unittests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182217 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 19:44:56 +00:00
Jakob Stoklund Olesen
00ce0f6512 Handle i64 FrameIndex nodes in SPARC v9 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 19:14:24 +00:00
Tim Northover
675b9e9f3d AArch64: make RuntimeDyld relocations idempotent
AArch64 ELF uses .rela relocations so there's no need to actually make
use of the bits we're setting in the destination  However, we should
make sure all bits are cleared properly since multiple runs of
resolveRelocations are possible and these could combine to produce
invalid results if stale versions remain in the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182214 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 15:39:03 +00:00
Tim Northover
820b147493 Invalidate instruction cache when setting memory to be executable.
lli's remote MCJIT code calls setExecutable just prior to running
code. In line with Darwin behaviour this seems to be the place to
invalidate any caches needed so that relocations can take effect
properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 15:28:16 +00:00
Bob Wilson
ff9a6b44e0 Temporarily disable this test because it is failing when using libc++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 14:59:08 +00:00
Benjamin Kramer
ebe7a52a17 Move the remaining simplify-libcalls tests to instcombine, merging most of them into a single file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182211 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 13:28:39 +00:00
Tim Northover
a73a6141ca Print uint64_t -debug text correctly on 32-bit hosts
On 32-bit hosts %p can print garbage when given a uint64_t, we should
use %llx instead. This only affects the output of the debugging text
produced by lli.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-19 09:55:06 +00:00
Renato Golin
6d65f333a3 Unsupported remote JIT on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 19:42:07 +00:00
David Majnemer
cb9d4667b7 isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.
This is useful if something that looks like (x & (1 << y)) ? 64 : 32 is
the divisor in a modulo operation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 19:30:37 +00:00
Arnold Schwaighofer
688b5103eb LoopVectorize: Handle single edge PHIs
We might encouter single edge PHIs - handle them with an identity select.

Fixes PR15990.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 18:38:34 +00:00
Dmitri Gribenko
edc399aceb docs/Passes: fix some typos
Patch by Yacine Belkadi.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182197 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 18:01:44 +00:00
Benjamin Kramer
769b70ec4f Add basic support for ELF32-ppc relocations to llvm-dwarfdump.
Should help the ppc32 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182194 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 16:00:35 +00:00
Hal Finkel
bf0bc3b2a2 Check InlineAsm clobbers in PPCCTRLoops
We don't need to reject all inline asm as using the counter register (most does
not). Only those that explicitly clobber the counter register need to prevent
the transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 09:20:39 +00:00
Tim Northover
9f61e485e6 AArch64: add CMake dependency to fix very parallel builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 08:17:47 +00:00
David Majnemer
8a55c2ecd4 X86: Bad peephole interaction between adc, MOV32r0
The peephole tries to reorder MOV32r0 instructions such that they are
before the instruction that modifies EFLAGS.

The problem is that the peephole does not consider the case where the
instruction that modifies EFLAGS also depends on the previous state of
EFLAGS.

Instead, walk backwards until we find an instruction that has a def for
EFLAGS but does not have a use.
If we find such an instruction, insert the MOV32r0 before it.
If it cannot find such an instruction, skip the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 01:02:03 +00:00
Matt Arsenault
24623dcd24 Remove duplicated comment
The same comment is already made in the header

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 00:24:09 +00:00