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7912 Commits

Author SHA1 Message Date
Evan Cheng
12914380ed Fix a typo pointd out by Maarten ter Huurne. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41059 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 23:27:11 +00:00
Dan Gohman
badb2d23d1 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41049 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 20:03:06 +00:00
Chris Lattner
a45d9a15ba Fix PR1607 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41048 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-13 18:42:37 +00:00
Chris Lattner
ace2e8ad0c expand a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41021 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-11 18:19:07 +00:00
Chris Lattner
384f4a94f8 With evan's explicit flag representation, hopefully we will finally be 
able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41020 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-11 18:16:46 +00:00
Bill Wendling
01284b4d55 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment. 
Make a 'memop' pattern just for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41017 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-11 09:52:53 +00:00
Christopher Lamb
a1eb155e52 Use subregs to improve any_extend code generation when feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41013 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 22:22:41 +00:00
Christopher Lamb
c59e52108b Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41010 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:48:46 +00:00
Christopher Lamb
6f41435879 Edit README in light of previous LEA16 commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41009 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:29:05 +00:00
Christopher Lamb
b81337117c Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 21:18:25 +00:00
Rafael Espindola
594d37e21a propagate struct size and alignment of byval arguments to the DAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40986 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 14:44:42 +00:00
Bill Wendling
ae9671b838 For kicks, I though it would be fun to use the correct opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40985 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 09:00:17 +00:00
Bill Wendling
76d708b76f Adding SSSE3 intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-10 06:22:27 +00:00
Evan Cheng
a3231ba237 Temporarily backing out this change until we know why some dejagnu tests are failing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40973 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 22:25:35 +00:00
Evan Cheng
f7ef26e701 divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40972 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 21:59:35 +00:00
Evan Cheng
a333b41af9 GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40970 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 18:05:17 +00:00
Dale Johannesen
5411a3937f long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40958 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 01:04:01 +00:00
Dale Johannesen
48bd15ed72 Fix arguments for some Altivec instructions. From SWB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40957 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-09 00:49:19 +00:00
Dale Johannesen
84109cd015 Fix spelling of mtvscr and mfvscr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40908 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 23:08:00 +00:00
Dale Johannesen
cdbe4d3ebe Long double patch 8 of N: make it partially work in 
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40906 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 20:29:26 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Dale Johannesen
a996d52e37 Long double patch 7 of N, unless I lost count:). 
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40886 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:17:37 +00:00
Dale Johannesen
9989a65693 Replace 4-line function with 10-line version per review comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 22:10:35 +00:00
Dale Johannesen
27f92be8b7 Move lengthy conditional down 1 level per review comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40878 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 21:48:35 +00:00
Dale Johannesen
6a30811d5c Get X86 long double calling convention to work 
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40877 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 21:31:06 +00:00
Dale Johannesen
88835735f4 Make 80-bit store maintain simulated FP stack correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40868 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 19:50:32 +00:00
Reid Spencer
181b6c9cb5 Fix minor doxygen nits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40854 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-05 20:06:04 +00:00
Dale Johannesen
59a587337e Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-05 18:49:15 +00:00
Chandler Carruth
6994040a95 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-04 01:51:18 +00:00
Dale Johannesen
8c78a26955 Make x86 long double alignment 32 for everything but 
Darwin (which makes size within a struct==96)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40796 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 22:46:15 +00:00
Dale Johannesen
8c1e6a119a long double patch 2 of N. Handle it in TargetData. 
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40792 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 20:20:50 +00:00
Chris Lattner
107f54a002 add an observation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40772 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-03 00:17:42 +00:00
Dan Gohman
61e729e2e9 More explicit keywords. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:21:54 +00:00
Dan Gohman
7f55fcbc6b Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40756 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:17:01 +00:00
Dan Gohman
f3372d1d64 Fix pastos in vector arithmetic intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40754 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 21:06:40 +00:00
Dan Gohman
73a902b228 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40736 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 14:27:55 +00:00
Evan Cheng
7afa166c76 Switch some multiplication instructions over to the new scheme for testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40723 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-02 05:48:35 +00:00
Evan Cheng
5278784621 Can't handle offset and scale if rip-relative addressing is to be used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40703 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:46:47 +00:00
Evan Cheng
0db079e2e6 Mac OS X X86-64 low 4G address not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40702 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:46:10 +00:00
Evan Cheng
f6844ca0e4 Mac OS X X86-64 low 4G address not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:45:51 +00:00
Evan Cheng
caf778ab3b Some out operands were incorrectly specified as input operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40697 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:07:38 +00:00
Evan Cheng
c5dd54154a Missing Requires. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40691 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 21:42:24 +00:00
Evan Cheng
1c3017c51e Be more precise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40689 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 20:22:37 +00:00
Dan Gohman
a9f643432d Change a .size directive to use a tab instead of a space, for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40672 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 14:42:30 +00:00
Evan Cheng
7fc77611ef Indexed loads each has 2 outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 00:12:08 +00:00
Dan Gohman
b1576f56c8 Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 20:11:57 +00:00
Evan Cheng
c64a1a921c Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 08:04:03 +00:00
Evan Cheng
4ebcc8c2f8 This isn't safe when there are uses of load's chain result. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40617 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 06:21:44 +00:00
Dan Gohman
825811dc83 Use tabs more consistently in assembler pseudo-ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40594 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 15:08:02 +00:00
Dan Gohman
fb71d38247 Fix the comment for getClosestTargetForJIT to reflect the fact that 
it does not have a Module parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40590 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-30 14:58:59 +00:00