llvm-6502/lib/CodeGen
Jakob Stoklund Olesen af06825460 Remove final verification in RABasic.
We now have a proper machine code verifier pass between register
allocation and rewriting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15 23:48:48 +00:00
..
AsmPrinter Allocate the contents of DwarfDebug's StringMaps in a single big BumpPtrAllocator. 2012-06-09 10:34:15 +00:00
SelectionDAG Make comment slightly more helpful. 2012-06-14 20:37:15 +00:00
AggressiveAntiDepBreaker.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
AllocationOrder.h Fix old doxygen comment. 2012-01-24 18:09:18 +00:00
Analysis.cpp quick fix for PR13006, will check in testcase later. 2012-06-01 15:02:52 +00:00
AntiDepBreaker.h
BranchFolding.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
BranchFolding.h
CalcSpillWeights.cpp Stop using LiveIntervals::isReMaterializable(). 2012-06-05 01:06:12 +00:00
CallingConvLower.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
CMakeLists.txt Sketch a LiveRegMatrix analysis pass. 2012-06-09 02:13:10 +00:00
CodeGen.cpp Reintroduce VirtRegRewriter. 2012-06-08 23:44:45 +00:00
CodePlacementOpt.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
CriticalAntiDepBreaker.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
CriticalAntiDepBreaker.h Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
DeadMachineInstructionElim.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
DFAPacketizer.cpp Target independent Hexagon Packetizer fix. 2012-05-01 21:28:30 +00:00
DwarfEHPrepare.cpp Relax the requirement that the exception object must be an instruction. During 2012-05-17 17:59:51 +00:00
EdgeBundles.cpp Twinify GraphWriter a little bit. 2011-11-15 16:26:38 +00:00
ExecutionDepsFix.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
ExpandISelPseudos.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
ExpandPostRAPseudos.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
GCMetadata.cpp Add 'llvm_unreachable' to passify GCC's understanding of the constraints 2012-01-10 18:08:01 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 2012-02-19 11:37:01 +00:00
IfConversion.cpp Start implementing pre-ra if-converter: using speculation and selects to eliminate branches. 2012-06-08 21:53:50 +00:00
InlineSpiller.cpp Print out register number in InlineSpiller. 2012-06-15 23:47:09 +00:00
InterferenceCache.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
InterferenceCache.h Add register mask support to InterferenceCache. 2012-02-10 18:58:34 +00:00
IntrinsicLowering.cpp Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics. 2012-01-31 01:58:48 +00:00
JITCodeEmitter.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
LatencyPriorityQueue.cpp misched preparation: rename core scheduler methods for consistency. 2012-03-07 23:00:49 +00:00
LexicalScopes.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
LiveDebugVariables.cpp Handle NewReg==OldReg in renameRegister(). 2012-05-15 22:20:27 +00:00
LiveDebugVariables.h
LiveInterval.cpp Simplify LiveInterval::print(). 2012-06-05 22:51:54 +00:00
LiveIntervalAnalysis.cpp Remove dead debug option -disable-rematerialization. 2012-06-06 16:22:41 +00:00
LiveIntervalUnion.cpp Move LiveUnionArray into LiveIntervalUnion.h 2012-06-05 23:57:30 +00:00
LiveIntervalUnion.h Move LiveUnionArray into LiveIntervalUnion.h 2012-06-05 23:57:30 +00:00
LiveRangeCalc.cpp Implement LiveRangeCalc::extendToUses() and createDeadDefs(). 2012-06-05 21:54:09 +00:00
LiveRangeCalc.h Implement LiveRangeCalc::extendToUses() and createDeadDefs(). 2012-06-05 21:54:09 +00:00
LiveRangeEdit.cpp Only erase virtregs with no uses left. 2012-05-22 14:52:12 +00:00
LiveRegMatrix.cpp Accept null PhysReg arguments to checkRegMaskInterference. 2012-06-15 22:24:22 +00:00
LiveRegMatrix.h Accept null PhysReg arguments to checkRegMaskInterference. 2012-06-15 22:24:22 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
LLVMTargetMachine.cpp Plug a leak when using MCJIT. 2012-05-20 17:24:08 +00:00
LocalStackSlotAllocation.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineBasicBlock.cpp Remove assignments which aren't used afterwards. 2012-06-15 19:30:42 +00:00
MachineBlockFrequencyInfo.cpp Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 2011-12-20 20:03:10 +00:00
MachineBlockPlacement.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
MachineBranchProbabilityInfo.cpp Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 2011-12-20 20:03:10 +00:00
MachineCodeEmitter.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
MachineCopyPropagation.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineCSE.cpp Switch some getAliasSet clients to MCRegAliasIterator. 2012-06-01 20:36:54 +00:00
MachineDominators.cpp
MachineFunction.cpp Teach CodeGen's version of computeMaskedBits to understand the range metadata. 2012-03-31 18:14:00 +00:00
MachineFunctionAnalysis.cpp Sink codegen optimization level into MCCodeGenInfo along side relocation model 2011-11-16 08:38:26 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Add an insertPass API to TargetPassConfig. <rdar://problem/11498613> 2012-05-30 00:17:12 +00:00
MachineInstr.cpp MachineInstr::eraseFromParent fix for removing bundled instrs. 2012-06-05 21:44:23 +00:00
MachineInstrBundle.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineLICM.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp
MachineModuleInfo.cpp Properly emit _fltused with FastISel. Refactor to share code with SDAG. 2012-02-22 19:06:13 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp Allow targets to select the default scheduler by name. 2012-04-19 01:34:10 +00:00
MachineRegisterInfo.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineScheduler.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
MachineSink.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
MachineSSAUpdater.cpp More dead code removal (using -Wunreachable-code) 2012-01-20 21:51:11 +00:00
MachineVerifier.cpp Make machine verifier check the first instruction of the last bundle instead of 2012-06-14 20:51:13 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
Passes.cpp Reintroduce VirtRegRewriter. 2012-06-08 23:44:45 +00:00
PeepholeOptimizer.cpp Revert r157755. 2012-06-06 23:53:03 +00:00
PHIElimination.cpp RegAlloc superpass: includes phi elimination, coalescing, and scheduling. 2012-02-10 04:10:36 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
ProcessImplicitDefs.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
PrologEpilogInserter.cpp Remove extra space. 2012-05-30 18:47:55 +00:00
PrologEpilogInserter.h Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
PseudoSourceValue.cpp More dead code removal (using -Wunreachable-code) 2012-01-20 21:51:11 +00:00
README.txt
RegAllocBase.cpp Also compute MBB live-in lists in the new rewriter pass. 2012-06-09 00:14:47 +00:00
RegAllocBase.h Also compute MBB live-in lists in the new rewriter pass. 2012-06-09 00:14:47 +00:00
RegAllocBasic.cpp Remove final verification in RABasic. 2012-06-15 23:48:48 +00:00
RegAllocFast.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
RegAllocGreedy.cpp Also compute MBB live-in lists in the new rewriter pass. 2012-06-09 00:14:47 +00:00
RegAllocPBQP.cpp Also compute MBB live-in lists in the new rewriter pass. 2012-06-09 00:14:47 +00:00
RegisterClassInfo.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
RegisterCoalescer.cpp Use regunit liveness in RegisterCoalescer when it is available. 2012-06-15 17:36:48 +00:00
RegisterCoalescer.h Remove unused private fields found by clang's new -Wunused-private-field. 2012-06-06 18:25:08 +00:00
RegisterPressure.cpp misched: When querying RegisterPressureTracker, always save current and max pressure. 2012-06-11 23:42:23 +00:00
RegisterScavenging.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
RenderMachineFunction.cpp Fix typo in ruler. No functionality change. 2012-01-03 18:22:43 +00:00
RenderMachineFunction.h
ScheduleDAG.cpp sched: Avoid trivially redundant DAG edges. Take the one with higher latency. 2012-06-13 02:39:00 +00:00
ScheduleDAGInstrs.cpp misched: disable SSA check pending PR13112. 2012-06-14 17:48:49 +00:00
ScheduleDAGPrinter.cpp Cleanup in preparation for misched: Move DAG visualization logic. 2012-03-07 00:18:22 +00:00
ScoreboardHazardRecognizer.cpp misched: Added MultiIssueItineraries. 2012-06-05 03:44:40 +00:00
ShadowStackGC.cpp [unwind removal] We no longer have 'unwind' instructions being generated, so 2012-02-06 21:16:41 +00:00
ShrinkWrapping.cpp Expose TargetPassConfig to PEI Pass 2012-02-06 22:51:18 +00:00
SjLjEHPrepare.cpp Revert r152705, which reapplied r152486 as this appears to be causing failures 2012-03-16 01:04:00 +00:00
SlotIndexes.cpp Remove more dead code. 2012-04-25 18:01:30 +00:00
Spiller.cpp Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 2012-04-02 22:44:18 +00:00
Spiller.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SpillPlacement.cpp Give a small negative bias to giant edge bundles. 2012-05-21 03:11:23 +00:00
SpillPlacement.h
SplitKit.cpp Pass context pointers to LiveRangeCalc::reset(). 2012-06-04 18:21:16 +00:00
SplitKit.h Make SplitAnalysis::UseSlots private. 2012-01-12 17:53:44 +00:00
StackProtector.cpp Enable stack protectors for all arrays, not just char arrays. rdar://5875909 2011-11-23 07:13:56 +00:00
StackSlotColoring.cpp StackSlotColoring does not use a VirtRegMap 2012-02-21 04:51:19 +00:00
StrongPHIElimination.cpp Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 2012-02-19 11:37:01 +00:00
TailDuplication.cpp Stop leaking RegScavengers from TailDuplication. 2012-06-06 13:53:41 +00:00
TargetFrameLoweringImpl.cpp Move parts of lib/Target that use CodeGen into lib/CodeGen. 2011-12-15 22:58:58 +00:00
TargetInstrInfoImpl.cpp TargetInstrInfo hooks implemented in codegen should be declared pure virtual. 2012-06-08 21:52:38 +00:00
TargetLoweringObjectFileImpl.cpp Look for the 'Is Simulated' module flag. This indicates that the program is compiled to run on a simulator. 2012-04-24 11:03:50 +00:00
TargetOptionsImpl.cpp Move parts of lib/Target that use CodeGen into lib/CodeGen. 2011-12-15 22:58:58 +00:00
TwoAddressInstructionPass.cpp misched: API for minimum vs. expected latency. 2012-06-05 21:11:27 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Also compute MBB live-in lists in the new rewriter pass. 2012-06-09 00:14:47 +00:00
VirtRegMap.h Reintroduce VirtRegRewriter. 2012-06-08 23:44:45 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.