llvm-6502/test/CodeGen/Mips
Chandler Carruth d24d326705 [SDAG] Introduce a combined set to the DAG combiner which tracks nodes
which have successfully round-tripped through the combine phase, and use
this to ensure all operands to DAG nodes are visited by the combiner,
even if they are only added during the combine phase.

This is critical to have the combiner reach nodes that are *introduced*
during combining. Previously these would sometimes be visited and
sometimes not be visited based on whether they happened to end up on the
worklist or not. Now we always run them through the combiner.

This fixes quite a few bad codegen test cases lurking in the suite while
also being more principled. Among these, the TLS codegeneration is
particularly exciting for programs that have this in the critical path
like TSan-instrumented binaries (although I think they engineer to use
a different TLS that is faster anyways).

I've tried to check for compile-time regressions here by running llc
over a merged (but not LTO-ed) clang bitcode file and observed at most
a 3% slowdown in llc. Given that this is essentially a worst case (none
of opt or clang are running at this phase) I think this is tolerable.
The actual LTO case should be even less costly, and the cost in normal
compilation should be negligible.

With this combining logic, it is possible to re-legalize as we combine
which is necessary to implement PSHUFB formation on x86 as
a post-legalize DAG combine (my ultimate goal).

Differential Revision: http://reviews.llvm.org/D4638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 22:15:28 +00:00
..
cconv [mips] Emit two CFI offset directives per double precision SDC1/LDC1 2014-07-10 22:23:30 +00:00
Fast-ISel Add load/store functionality 2014-06-16 22:05:47 +00:00
llvm-ir [mips][mips64r6] Use JALR for indirect branches instead of JR (which is not available on MIPS32r6/MIPS64r6) 2014-07-09 10:21:59 +00:00
mips32r6 [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 2014-05-09 09:46:21 +00:00
mips64r6 [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 2014-05-09 09:46:21 +00:00
msa ps][mips64r6] Added LSA/DLSA instructions 2014-06-20 09:28:09 +00:00
2008-06-05-Carry.ll
2008-07-03-SRet.ll
2008-07-06-fadd64.ll
2008-07-07-Float2Int.ll
2008-07-07-FPExtend.ll
2008-07-07-IntDoubleConvertions.ll
2008-07-15-InternalConstant.ll
2008-07-15-SmallSection.ll
2008-07-16-SignExtInReg.ll
2008-07-22-Cstpool.ll
2008-07-23-fpcmp.ll
2008-07-29-icmp.ll
2008-07-31-fcopysign.ll
2008-08-01-AsmInline.ll [mips][mips64r6] Improve tests affected by the changes to multiplies and divides 2014-06-11 15:48:00 +00:00
2008-08-03-fabs64.ll
2008-08-03-ReturnDouble.ll
2008-08-04-Bitconvert.ll
2008-08-06-Alloca.ll
2008-08-07-CC.ll
2008-08-07-FPRound.ll
2008-08-08-bswap.ll
2008-08-08-ctlz.ll
2008-10-13-LegalizerBug.ll
2008-11-10-xint_to_fp.ll
2009-11-16-CstPoolLoad.ll [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler. 2014-02-20 14:58:19 +00:00
2010-07-20-Switch.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
2010-11-09-CountLeading.ll
2010-11-09-Mul.ll
2011-05-26-BranchKillsVreg.ll
2012-12-12-ExpandMemcpy.ll
2013-11-18-fp64-const0.ll [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 2014-06-12 11:55:58 +00:00
abicalls.ll [mips] Fix emission of '.option pic0' for MIPS-IV. 2014-04-16 13:58:57 +00:00
abiflags32.ll [mips] Do not emit '.module fp=...' unless we really need to. 2014-07-21 15:25:24 +00:00
abiflags-xx.ll [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is 2014-07-14 09:40:29 +00:00
addc.ll
addi.ll
addressing-mode.ll
align16.ll
alloca16.ll
alloca.ll
analyzebranch.ll [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions 2014-07-09 10:40:20 +00:00
and1.ll
asm-large-immediate.ll
atomic.ll Replace the result usages while legalizing cmpxchg. 2014-07-21 17:33:44 +00:00
atomicops.ll IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
beqzc1.ll
beqzc.ll
biggot.ll
blez_bgez.ll [mips] Make mips64 the default CPU for the mips64 architecture 2014-02-20 13:13:33 +00:00
blockaddr.ll [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler. 2014-02-20 14:58:19 +00:00
br-jmp.ll
brconeq.ll
brconeqk.ll
brconeqz.ll
brconge.ll
brcongt.ll
brconle.ll
brconlt.ll
brconne.ll
brconnek.ll
brconnez.ll
brdelayslot.ll
brind.ll
brsize3.ll
brsize3a.ll
bswap.ll [mips] Check emitted code for llvm.bswap.i32 on MIPS16/MIPS64 and llvm.bswap.i64 on MIPS16. 2014-03-31 11:00:04 +00:00
buildpairextractelementf64.ll [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves 2014-07-14 12:41:31 +00:00
cache-intrinsic.ll Add @llvm.clear_cache builtin 2014-03-26 12:52:28 +00:00
call-optimization.ll
cfi_offset.ll [mips] Emit two CFI offset directives per double precision SDC1/LDC1 2014-07-10 22:23:30 +00:00
check-noat.ll
ci2.ll
cmov.ll [SDAG] Introduce a combined set to the DAG combiner which tracks nodes 2014-07-24 22:15:28 +00:00
cmplarge.ll
const1.ll
const4a.ll
const6.ll
const6a.ll
const-mult.ll [mips] Make mips64 the default CPU for the mips64 architecture 2014-02-20 13:13:33 +00:00
constantfp0.ll
countleading.ll [mips][mips64r6] Correct select patterns that have the condition or true/false values backwards 2014-07-09 10:47:26 +00:00
cprestore.ll
ctlz.ll
DbgValueOtherTargets.test
disable-tail-merge.ll
div_rem.ll
div.ll
divrem.ll [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. 2014-06-12 10:44:10 +00:00
divu_remu.ll
divu.ll
double2int.ll
dsp-patterns-cmp-vselect.ll
dsp-patterns.ll
dsp-r1.ll [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6 2014-06-12 10:54:16 +00:00
dsp-r2.ll
dsp-vec-load-store.ll
eh-dwarf-cfa.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
eh-return32.ll [mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6) 2014-07-09 10:16:07 +00:00
eh-return64.ll [mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6) 2014-07-09 10:16:07 +00:00
eh.ll
ehframe-indirect.ll Fix MIPS exception personality encoding. 2014-05-30 16:48:56 +00:00
elf_eflags.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
emit-big-cst.ll
ex2.ll
extins.ll
f16abs.ll
fabs.ll Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math 2014-04-09 09:56:43 +00:00
fastcc.ll [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl. 2014-02-07 17:16:40 +00:00
fcmp.ll Make it possible for ints/floats to return different values from getBooleanContents() 2014-07-10 10:18:12 +00:00
fcopysign-f32-f64.ll [mips] Fix fcopysign for MIPS-IV and add the test. 2014-04-14 16:24:12 +00:00
fcopysign.ll [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 2014-06-12 11:55:58 +00:00
fixdfsf.ll
fmadd1.ll [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 2014-06-12 11:55:58 +00:00
fneg.ll Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math 2014-04-09 09:56:43 +00:00
fp16instrinsmc.ll
fp16mix.ll
fp16static.ll
fp64a.ll [mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1. 2014-07-14 13:08:14 +00:00
fp-indexed-ls.ll [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 2014-06-12 14:19:28 +00:00
fp-spill-reload.ll
fpbr.ll [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 2014-06-12 15:00:17 +00:00
fpneeded.ll
fpnotneeded.ll
fptr2.ll
fpxx.ll [mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1. 2014-07-14 13:08:14 +00:00
frame-address.ll
frem.ll
global-address.ll [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler. 2014-02-20 14:58:19 +00:00
global-pointer-reg.ll
gpreg-lazy-binding.ll
gprestore.ll
helloworld.ll
hf1_body.ll
hf16_1.ll
hf16call32_body.ll
hf16call32.ll
hfptrcall.ll
i32k.ll
i64arg.ll
imm.ll
indirectcall.ll
init-array.ll
inlineasm64.ll
inlineasm_constraint.ll [mips] Change lwl and lwr in inlineasm_constraint.ll to lw 2014-05-22 11:51:06 +00:00
inlineasm-cnstrnt-bad-I-1.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-J.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-K.ll
inlineasm-cnstrnt-bad-L.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-N.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-O.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-bad-P.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-reg64.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasm-cnstrnt-reg.ll [mips][mips64r6] Improve tests affected by the changes to multiplies and divides 2014-06-11 15:48:00 +00:00
inlineasm-operand-code.ll [mips] Use addiu in inline assembly tests since addi is not available in all ISA's 2014-05-22 11:46:58 +00:00
inlineasmmemop.ll
int-to-float-conversion.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
internalfunc.ll
jtstat.ll
l3mc.ll This patch has two main functions: 2014-02-14 19:16:39 +00:00
largeimm1.ll
largeimmprinting.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
lazy-binding.ll
lb1.ll
lbu1.ll
lcb2.ll
lcb3c.ll
lcb4a.ll
lcb5.ll
lh1.ll
lhu1.ll
lit.local.cfg Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
llcarry.ll
load-store-left-right.ll [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 2014-05-23 13:18:02 +00:00
longbranch.ll [mips] Modify long branch for NaCl: 2014-06-05 13:52:08 +00:00
machineverifier.ll
madd-msub.ll [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6 2014-06-12 10:54:16 +00:00
mature-mc-support.ll Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call 2014-02-13 14:44:26 +00:00
mbrsize4a.ll
memcpy.ll
micromips-atomic.ll Fixed operand of SC microMIPS instruction. 2014-02-28 18:22:56 +00:00
micromips-directives.ll [mips] Emit '.set nomicromips' before a function's entry label 2014-04-16 11:46:59 +00:00
micromips-jal.ll Fixed issue with microMIPS JAL instruction. 2014-03-31 14:00:10 +00:00
micromips-load-effective-address.ll
mips16_32_1.ll
mips16_32_3.ll
mips16_32_4.ll
mips16_32_5.ll
mips16_32_6.ll
mips16_32_7.ll
mips16_32_8.ll
mips16_32_9.ll
mips16_32_10.ll
mips16_fpret.ll
mips16-hf-attr.ll
mips16ex.ll Print a=b as an assignment. 2014-06-24 22:45:16 +00:00
mips16fpe.ll
mips64-f128-call.ll
mips64-f128.ll [mips][mips64r6] Correct select patterns that have the condition or true/false values backwards 2014-07-09 10:47:26 +00:00
mips64-libcall.ll
mips64-sret.ll Allow sret on the second parameter as well as the first 2014-05-09 22:32:13 +00:00
mips64directive.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64ext.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64extins.ll
mips64fpimm0.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64fpldst.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64imm.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64instrs.ll [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 2014-06-16 13:18:59 +00:00
mips64intldst.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64lea.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
mips64muldiv.ll [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. 2014-06-12 10:44:10 +00:00
mips64shift.ll
mipslopat.ll
misha.ll
mno-ldc1-sdc1.ll [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves 2014-07-14 12:41:31 +00:00
mul.ll
mulll.ll
mulull.ll
nacl-align.ll Moved test file from test/MC/Mips to test/CodeGen/Mips. 2014-03-07 22:08:46 +00:00
nacl-branch-delay.ll [mips] Implement NaCl sandboxing of loads, stores and SP changes: 2014-03-10 20:34:23 +00:00
nacl-reserved-regs.ll [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl. 2014-02-07 17:16:40 +00:00
neg1.ll
no-odd-spreg.ll [mips] Do not emit '.module [no]oddspreg' unless we really need to. 2014-07-21 10:45:47 +00:00
nomips16.ll
not1.ll
null-streamer.ll [Mips] Add a target streamer when creating a null streamer. 2014-06-23 19:43:40 +00:00
null.ll
o32_cc_byval.ll
o32_cc_vararg.ll
o32_cc.ll [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves 2014-07-14 12:41:31 +00:00
octeon_popcnt.ll [MIPS] Add cpu octeon and some instructions 2014-03-20 11:51:58 +00:00
octeon.ll [mips] Add more Octeon cnMips instructions 2014-04-02 18:40:43 +00:00
optimize-fp-math.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
optimize-pic-o0.ll Fix regression with -O0 for mips . 2014-03-10 16:31:25 +00:00
or1.ll
powif64_16.ll
prevent-hoisting.ll Prevent hoisting the instruction whose def might be clobbered by the terminator. 2014-06-05 13:42:48 +00:00
private.ll
ra-allocatable.ll
rdhwr-directives.ll
rem.ll
remat-immed-load.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
remu.ll
return_address.ll
return-vector.ll
rotate.ll
s2rem.ll
sb1.ll
sel1c.ll
sel2c.ll
select.ll Make it possible for ints/floats to return different values from getBooleanContents() 2014-07-10 10:18:12 +00:00
selectcc.ll [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 2014-06-12 13:39:06 +00:00
seleq.ll
seleqk.ll
selgek.ll
selgt.ll
selle.ll
selltk.ll
selne.ll
selnek.ll
selpat.ll
selTBteqzCmpi.ll
selTBtnezCmpi.ll
selTBtnezSlti.ll
setcc-se.ll
seteq.ll
seteqz.ll
setge.ll
setgek.ll
setle.ll
setlt.ll
setltk.ll
setne.ll
setuge.ll
setugt.ll
setule.ll
setult.ll
setultk.ll
sh1.ll
shift-parts.ll
simplebr.ll
sint-fp-store_pattern.ll [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point 2014-04-14 16:00:28 +00:00
sitofp-selectcc-opt.ll
sll1.ll
sll2.ll
small-section-reserve-gp.ll
spill-copy-acreg.ll
sr1.ll
sra1.ll
sra2.ll
srl1.ll
srl2.ll
stack-alignment.ll
stackcoloring.ll
stacksize.ll
start-asm-file.ll [mips] Add initial support for NaN2008 in the back-end. 2014-04-16 15:48:55 +00:00
stchar.ll
stldst.ll
sub1.ll
sub2.ll
swzero.ll
tail16.ll
tailcall.ll
tls16_2.ll
tls16.ll
tls-alias.ll [pr19844] Add thread local mode to aliases. 2014-05-28 18:15:43 +00:00
tls-models.ll
tls.ll Add extra CHECK prefix to tests with explicit prefix 2014-02-16 13:28:15 +00:00
tnaked.ll
trap1.ll
trap.ll
uitofp.ll
ul1.ll
unalignedload.ll [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 2014-05-23 13:18:02 +00:00
vector-load-store.ll
vector-setcc.ll
weak.ll
xor1.ll
zeroreg.ll [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 2014-06-12 13:39:06 +00:00