Vincent Lejeune 26db9ecfac R600: Do not mergevector after a vector reg is used ... If we merge vector when a vector is used, it will generate an artificial antidependency that can prevent 2 tex/vtx instructions to use the same clause and thus generate extra clauses that reduce performance. There is no test case as such situation is really hard to predict. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187516 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-31 19:32:12 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
AMDGPU.h	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
AMDGPU.td
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp	R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary	2013-07-23 23:54:56 +00:00
AMDGPUISelLowering.cpp	R600/SI: Expand vector fp <-> int conversions	2013-07-30 14:31:03 +00:00
AMDGPUISelLowering.h	DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free	2013-07-23 23:55:03 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
AMDGPUTargetMachine.h	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
AMDILBase.td
AMDILCFGStructurizer.cpp	R600: Remove predicated_break inst	2013-07-31 19:31:14 +00:00
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelLowering.cpp
AMDILRegisterInfo.td
CMakeLists.txt	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ControlFlowFinalizer.cpp	R600: Remove predicated_break inst	2013-07-31 19:31:14 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp	R600: Remove predicated_break inst	2013-07-31 19:31:14 +00:00
R600InstrFormats.td	R600: Use SchedModel enum for is{Trans,Vector}Only functions	2013-07-31 19:31:35 +00:00
R600InstrInfo.cpp	R600: Avoid more than 4 literals in the same instruction group at scheduling	2013-07-31 19:32:07 +00:00
R600InstrInfo.h	R600: Use SchedModel enum for is{Trans,Vector}Only functions	2013-07-31 19:31:35 +00:00
R600Instructions.td	R600: Use SchedModel enum for is{Trans,Vector}Only functions	2013-07-31 19:31:35 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600/SI: Expand vector fp <-> int conversions	2013-07-30 14:31:03 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp	R600: Non vector only instruction can be scheduled on trans unit	2013-07-31 19:31:56 +00:00
R600MachineScheduler.h	R600: Non vector only instruction can be scheduled on trans unit	2013-07-31 19:31:56 +00:00
R600OptimizeVectorRegisters.cpp	R600: Do not mergevector after a vector reg is used	2013-07-31 19:32:12 +00:00
R600Packetizer.cpp	R600: Non vector only instruction can be scheduled on trans unit	2013-07-31 19:31:56 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
SIAnnotateControlFlow.cpp
SIDefines.h
SIInsertWaits.cpp
SIInstrFormats.td
SIInstrInfo.cpp
SIInstrInfo.h
SIInstrInfo.td
SIInstructions.td	R600: Add support for 24-bit MAD instructions	2013-07-23 01:48:49 +00:00
SIIntrinsics.td
SIISelLowering.cpp
SIISelLowering.h
SILowerControlFlow.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td