llvm-6502/lib/CodeGen
2011-10-20 13:38:16 +00:00
..
AsmPrinter Missed a spot! 2011-10-18 22:40:18 +00:00
SelectionDAG Fix a type in the legalization of CONCAT_VECTORS. 2011-10-20 13:38:16 +00:00
AggressiveAntiDepBreaker.cpp Rename TargetSubtarget to TargetSubtargetInfo for consistency. 2011-07-01 21:01:15 +00:00
AggressiveAntiDepBreaker.h Rename TargetSubtarget to TargetSubtargetInfo for consistency. 2011-07-01 21:01:15 +00:00
AllocationOrder.cpp Rename TRI::getAllocationOrder() to getRawAllocationOrder(). 2011-06-16 23:31:16 +00:00
AllocationOrder.h Get allocation orders from RegisterClassInfo when possible. 2011-06-06 21:02:04 +00:00
Analysis.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
AntiDepBreaker.h Update DBG_VALUEs while breaking anti dependencies. 2011-06-02 21:26:52 +00:00
BranchFolding.cpp Fix liveness computations in BranchFolding. 2011-08-05 18:47:07 +00:00
BranchFolding.h When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). 2011-07-06 23:41:48 +00:00
CalcSpillWeights.cpp Move CalculateRegClass to MRI::recomputeRegClass. 2011-08-09 16:46:27 +00:00
CallingConvLower.cpp Rename the ParmContext enum values to make a bit more sense and add a small 2011-06-10 20:37:36 +00:00
CMakeLists.txt Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix. 2011-09-28 00:01:54 +00:00
CodeGen.cpp Rename BlockFrequency to BlockFrequencyInfo and MachineBlockFrequency to 2011-07-25 19:25:40 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. 2011-06-27 21:26:13 +00:00
CriticalAntiDepBreaker.h Teach antidependency breakers to use RegisterClassInfo. 2011-06-16 21:56:21 +00:00
DeadMachineInstructionElim.cpp Track live-out physical registers in MachineDCE. 2011-06-27 15:00:36 +00:00
DwarfEHPrepare.cpp Update the dominator tree with the correct dominator for the new 'unwind' block. 2011-08-26 21:36:12 +00:00
EdgeBundles.cpp Function::getNumBlockIDs() should be used instead of Function::size() to set the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix). 2011-06-16 00:03:21 +00:00
ELF.h
ELFCodeEmitter.cpp Fix asserts in CodeGen from: 2011-09-10 01:07:54 +00:00
ELFCodeEmitter.h Fix asserts in CodeGen from: 2011-09-10 01:07:54 +00:00
ELFWriter.cpp Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 2011-07-20 19:50:42 +00:00
ELFWriter.h Fix a FIXME by making GlobalVariable::getInitializer() return a 2011-06-19 18:37:11 +00:00
ExecutionDepsFix.cpp Rename class and clean up source. 2011-09-28 00:01:56 +00:00
ExpandISelPseudos.cpp - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 2011-06-28 19:10:37 +00:00
ExpandPostRAPseudos.cpp Give targets a chance to expand even standard pseudos. 2011-10-10 20:34:28 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Fix typo in #include which revealed in the case-sensitive filesystem. 2011-08-03 22:53:41 +00:00
InlineSpiller.cpp Add value numbers when spilling dead defs. 2011-10-14 00:34:31 +00:00
InterferenceCache.cpp Allow null interference cursors to be queried. 2011-07-23 03:10:17 +00:00
InterferenceCache.h Allow null interference cursors to be queried. 2011-07-23 03:10:17 +00:00
IntrinsicLowering.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp Don't forget to reconstruct D after changing the scope that we're 2011-10-13 21:43:44 +00:00
LiveDebugVariables.cpp Namespacify. 2011-09-16 00:35:06 +00:00
LiveDebugVariables.h
LiveInterval.cpp Leave hasPHIKill flags alone in LiveInterval::RenumberValues. 2011-09-15 04:37:18 +00:00
LiveIntervalAnalysis.cpp Add a FIXME. 2011-10-05 16:51:21 +00:00
LiveIntervalUnion.cpp Simplify the interference checking code a bit. 2011-08-12 00:22:04 +00:00
LiveIntervalUnion.h Simplify the interference checking code a bit. 2011-08-12 00:22:04 +00:00
LiveRangeCalc.cpp Switch extendInBlock() to take a kill slot instead of the last use slot. 2011-09-13 16:47:56 +00:00
LiveRangeCalc.h Unbreak msvc. 2011-09-13 03:58:34 +00:00
LiveRangeEdit.cpp Move CalculateRegClass to MRI::recomputeRegClass. 2011-08-09 16:46:27 +00:00
LiveRangeEdit.h Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used. 2011-07-18 12:00:32 +00:00
LiveStackAnalysis.cpp Move getCommonSubClass() into TRI. 2011-09-30 22:18:51 +00:00
LiveVariables.cpp Silence a bunch (but not all) "variable written but not read" warnings 2011-08-12 14:54:45 +00:00
LLVMTargetMachine.cpp Add support for a new extension to the .file directive: 2011-10-17 23:05:28 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Update live-in lists when splitting critical edges. 2011-10-14 17:25:46 +00:00
MachineBlockFrequencyInfo.cpp Add more constantness in BlockFrequencyInfo. 2011-08-03 21:30:57 +00:00
MachineBranchProbabilityInfo.cpp Introduce MachineBranchProbabilityInfo class, which has similar API to 2011-06-16 20:22:37 +00:00
MachineCSE.cpp We need to verify that the machine instruction we're using as a replacement for 2011-10-12 23:03:40 +00:00
MachineDominators.cpp
MachineFunction.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Add missing braces to pacify GCC's -Wparentheses. 2011-10-13 00:54:59 +00:00
MachineLICM.cpp Constraint register class with constrainRegClass() to CSE a virtual into another. rdar://10293289 2011-10-17 19:50:12 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp
MachineModuleInfo.cpp Add an ivar that maps a landing pad's EH symbol to the call sites that may jump 2011-10-05 22:20:38 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Also inflate register classes around inline asm. 2011-10-12 23:37:40 +00:00
MachineSink.cpp While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 2011-09-07 00:07:58 +00:00
MachineSSAUpdater.cpp
MachineVerifier.cpp Fix sub-register operand verification. 2011-10-05 22:12:57 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp When deleting a phi cycle after looking through copies, constrain the register 2011-10-17 21:54:46 +00:00
Passes.cpp
PeepholeOptimizer.cpp If MI is deleted then remove it from the set. If a new MI is created, it could 2011-10-13 02:16:18 +00:00
PHIElimination.cpp Add an isSSA() flag to MachineRegisterInfo. 2011-07-29 22:51:22 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Rename TargetSubtarget to TargetSubtargetInfo for consistency. 2011-07-01 21:01:15 +00:00
ProcessImplicitDefs.cpp Handle REG_SEQUENCE with implicitly defined operands. 2011-07-28 21:38:51 +00:00
PrologEpilogInserter.cpp A few 80-col violations. 2011-10-14 20:36:23 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.h Switch AllocationOrder to using RegisterClassInfo instead of a BitVector 2011-06-03 20:34:53 +00:00
RegAllocBasic.cpp Privatize an unused part of the LiveIntervalUnion::Query interface. 2011-08-11 21:00:42 +00:00
RegAllocFast.cpp Better diagnostics when inline asm fails to allocate. 2011-07-02 07:17:37 +00:00
RegAllocGreedy.cpp Ignore the cloning of unknown registers. 2011-09-14 17:34:37 +00:00
RegAllocLinearScan.cpp Refer to the RegisterCoalescer pass by ID. 2011-08-09 00:29:53 +00:00
RegAllocPBQP.cpp Refer to the RegisterCoalescer pass by ID. 2011-08-09 00:29:53 +00:00
RegisterClassInfo.cpp Detect proper register sub-classes. 2011-08-05 21:28:14 +00:00
RegisterClassInfo.h Detect proper register sub-classes. 2011-08-05 21:28:14 +00:00
RegisterCoalescer.cpp Remove unused DstSubIdx argument. 2011-10-05 21:22:53 +00:00
RegisterCoalescer.h Rename member variables to follow coding standards. 2011-08-09 01:01:27 +00:00
RegisterScavenging.cpp Silence a bunch (but not all) "variable written but not read" warnings 2011-08-12 14:54:45 +00:00
RenderMachineFunction.cpp Add TargetRegisterInfo::getRawAllocationOrder(). 2011-06-16 17:42:25 +00:00
RenderMachineFunction.h
ScheduleDAG.cpp Make a bunch of symbols private. 2011-08-19 01:42:18 +00:00
ScheduleDAGEmit.cpp createMCInstPrinter doesn't need TargetMachine anymore. 2011-07-06 19:45:42 +00:00
ScheduleDAGInstrs.cpp PostRA scheduler fix. Clear stale loop dependencies. 2011-10-07 06:33:09 +00:00
ScheduleDAGInstrs.h PostRA scheduler fix. Clear stale loop dependencies. 2011-10-07 06:33:09 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Remove an invalid assert that is really just asserting when the scheduler emits 2011-09-27 21:59:16 +00:00
ShadowStackGC.cpp Use the C personality function instead of the C++ personality function. 2011-09-22 17:56:40 +00:00
ShrinkWrapping.cpp
SjLjEHPrepare.cpp Now Igor, throw the switch...give my creation life! 2011-10-17 22:26:23 +00:00
SlotIndexes.cpp
Spiller.cpp
Spiller.h
SpillPlacement.cpp Be more conservative when forming compact regions. 2011-08-03 23:09:38 +00:00
SpillPlacement.h Be more conservative when forming compact regions. 2011-08-03 23:09:38 +00:00
SplitKit.cpp Spill mode: Hoist back-copies locally. 2011-09-16 00:03:35 +00:00
SplitKit.h Hoist back-copies to the least busy dominator. 2011-09-14 16:45:39 +00:00
Splitter.cpp Refer to the RegisterCoalescer pass by ID. 2011-08-09 00:29:53 +00:00
Splitter.h
StackProtector.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
StackSlotColoring.cpp - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 2011-06-28 19:10:37 +00:00
StrongPHIElimination.cpp Use an existing method. 2011-10-13 07:36:41 +00:00
TailDuplication.cpp Trim an unneeded header. 2011-08-09 23:49:21 +00:00
TargetInstrInfoImpl.cpp Permit remat of partial register defs when it is safe. 2011-09-01 18:27:51 +00:00
TargetLoweringObjectFileImpl.cpp Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 2011-07-20 19:50:42 +00:00
TwoAddressInstructionPass.cpp PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that. 2011-09-23 22:41:57 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Also add <imp-use,kill> flags for redefined super-registers. 2011-10-05 00:01:48 +00:00
VirtRegMap.h Be more aggressive about following hints. 2011-07-08 20:46:18 +00:00
VirtRegRewriter.cpp - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 2011-06-28 19:10:37 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.