llvm-6502/lib/Target/PowerPC
Misha Brukman f5f70685b6 Disable PPC64 backend by default because LLC cannot choose automatically between
SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15688 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-12 17:16:43 +00:00
..
LICENSE.TXT Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I 2004-08-05 23:46:27 +00:00
Makefile Generate a code emitter for PowerPC as well, this will be used in the JIT. 2004-08-09 17:24:32 +00:00
PowerPC.td * Fix file header to use tablegen emacs mode instead of c++ 2004-08-10 21:24:44 +00:00
PowerPCInstrInfo.cpp Set the is64bit flag and propagate it to PowerPCRegisterInfo 2004-08-11 23:45:43 +00:00
PowerPCInstrInfo.h Set the is64bit flag and propagate it to PowerPCRegisterInfo 2004-08-11 23:45:43 +00:00
PowerPCPEI.cpp Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets 2004-08-10 22:47:03 +00:00
PowerPCRegisterInfo.cpp * Set the is64bit boolean flag in PowerPCRegisterInfo 2004-08-11 23:44:55 +00:00
PowerPCRegisterInfo.h * Set the is64bit boolean flag in PowerPCRegisterInfo 2004-08-11 23:44:55 +00:00
PowerPCTargetMachine.h * Move AIX into the llvm namespace to be accessed from RegisterInfo 2004-08-11 23:47:08 +00:00
PPC32AsmPrinter.cpp Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit. 2004-08-11 00:09:42 +00:00
PPC32ISelSimple.cpp Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
PPC32JITInfo.h Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
PPC64AsmPrinter.cpp * Print out full names for non-GPR or -FPR registers 2004-08-12 03:28:47 +00:00
PPC64CodeEmitter.cpp Breaking up the PowerPC target into 32- and 64-bit subparts: Part II: 64-bit. 2004-08-11 00:10:41 +00:00
PPC64ISelSimple.cpp * Correct 64-bit version: blr 1 (not 0) 2004-08-12 03:30:03 +00:00
PPC64JITInfo.h Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
PPC64TargetMachine.h Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
PPC.h 64-bit instruction selector and AIX-specific 64-bit asm printer 2004-08-11 23:42:15 +00:00
PPCAsmPrinter.cpp Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit. 2004-08-11 00:09:42 +00:00
PPCBranchSelector.cpp Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets 2004-08-10 22:47:03 +00:00
PPCCodeEmitter.cpp Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit. 2004-08-11 00:09:42 +00:00
PPCInstrBuilder.h * Wrap long lines (comments and code) 2004-07-07 20:01:36 +00:00
PPCInstrFormats.td Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes 2004-08-11 20:56:14 +00:00
PPCInstrInfo.td Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes 2004-08-11 23:33:34 +00:00
PPCJITInfo.h Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest. 2004-08-11 00:11:25 +00:00
PPCRegisterInfo.td Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64 2004-08-12 00:10:01 +00:00
PPCTargetMachine.cpp Disable PPC64 backend by default because LLC cannot choose automatically between 2004-08-12 17:16:43 +00:00
PPCTargetMachine.h Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
README.txt Fix casts of float to unsigned long 2004-08-10 20:42:36 +00:00

TODO:
* implement cast fp to bool
* implement signed right shift by reg
* fix ulong to double:
  floatdidf assumes signed longs.  so if the high but of a ulong
  just happens to be set, you get the wrong sign.  The fix for this
  is to call cmpdi2 to compare against zero, if so shift right by one,
  convert to fp, and multiply by (add to itself).  the sequence would
  look like:
  {r3:r4} holds ulong a;
  li r5, 0
  li r6, 0 (set r5:r6 to ulong 0)
  call cmpdi2 ==> sets r3 <, =, > 0
  if r3 > 0
  call floatdidf as usual
  else
  shift right ulong a, 1 (we could use emitShift)
  call floatdidf
  fadd f1, f1, f1 (fp left shift by 1)
* PowerPCPEI.cpp needs to be replaced by shiny new target hook
* setCondInst needs to know branchless versions of seteq/setne/etc
* cast elimination pass (uint -> sbyte -> short, kill the byte -> short)
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Current hacks:
* lazy insert of GlobalBaseReg definition at front of first MBB
  A prime candidate for sabre's future "slightly above ISel" passes.
* cast code is huge, unwieldy.  Should probably be broken up into
  smaller pieces.
* visitLoadInst is getting awfully cluttered as well.

Currently failing tests:
* SingleSource
  `- Regression
  |  `- casts (ulong to fp failure)
  `- Benchmarks
  |  `- Shootout-C++ : most programs fail, miscompilations
  `- UnitTests
  |  `- C++Catch
  |  `- SimpleC++Test
  |  `- ConditionalExpr (also C++)
* MultiSource
  |- Applications
  |  `- burg: miscompilation
  |  `- siod: llc bus error
  |  `- hbd: miscompilation
  |  `- d (make_dparser): miscompilation
  `- Benchmarks
     `- MallocBench/make: miscompilation