Colin LeMahieu 6194244842 [Hexagon] Factoring classes out of store patterns. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228602 91177308-0d34-0410-b5e6-96231b3b80d8

2015-02-09 20:33:46 +00:00

..

intrinsics

[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.

2015-02-03 20:40:52 +00:00

absaddr-store.ll

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absimm.ll

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adde.ll

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always-ext.ll

[Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet.

2015-02-04 17:52:06 +00:00

args.ll

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ashift-left-right.ll

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block-addr.ll

[Hexagon] Adding reg-reg indexed load forms.

2014-12-30 18:58:47 +00:00

BranchPredict.ll

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cext-check.ll

[Hexagon] Reapplying 224775 load words.

2014-12-23 20:02:16 +00:00

cext-valid-packet1.ll

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cext-valid-packet2.ll

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cmp_pred2.ll

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cmp_pred_reg.ll

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cmp_pred.ll

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cmp-to-genreg.ll

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cmp-to-predreg.ll

[Hexagon] Simplifying and formatting several patterns. Changing a pattern multiply to be expanded.

2015-02-05 21:13:25 +00:00

cmpb_pred.ll

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combine_ir.ll

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combine.ll

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convertdptoint.ll

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convertdptoll.ll

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convertsptoint.ll

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convertsptoll.ll

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ctlz-cttz-ctpop.ll

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ctor.ll

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dadd.ll

[Hexagon] Replacing old fadd/fsub instructions and updating references.

2015-01-15 16:30:07 +00:00

dmul.ll

[Hexagon] Deleting old float comparison instruction and updating references to new ones.

2015-01-15 17:28:14 +00:00

double.ll

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doubleconvert-ieee-rnd-near.ll

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dsub.ll

[Hexagon] Replacing old fadd/fsub instructions and updating references.

2015-01-15 16:30:07 +00:00

dualstore.ll

[Hexagon] Factoring classes out of store patterns.

2015-02-09 20:33:46 +00:00

extload-combine.ll

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fadd.ll

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fcmp.ll

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float.ll

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floatconvert-ieee-rnd-near.ll

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fmul.ll

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frame.ll

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fsub.ll

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fusedandshift.ll

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gp-plus-offset-load.ll

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gp-plus-offset-store.ll

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gp-rel.ll

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hwloop-cleanup.ll

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hwloop-const.ll

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hwloop-dbg.ll

IR: Move MDLocation into place

2015-01-14 22:27:36 +00:00

hwloop-le.ll

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hwloop-lt1.ll

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hwloop-lt.ll

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hwloop-ne.ll

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i1_VarArg.ll

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i8_VarArg.ll

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i16_VarArg.ll

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idxload-with-zero-offset.ll

[Hexagon] Updating indexed load-extend patterns and changing test to new expected output.

2015-01-15 21:07:52 +00:00

indirect-br.ll

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lit.local.cfg

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macint.ll

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memops1.ll

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memops2.ll

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memops3.ll

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memops.ll

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misaligned-access.ll

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mpy.ll

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newvaluejump2.ll

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newvaluejump.ll

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newvaluestore.ll

[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.

2014-12-29 20:44:51 +00:00

opt-fabs.ll

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opt-fneg.ll

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packetize_cond_inst.ll

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postinc-load.ll

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postinc-store.ll

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pred-absolute-store.ll

[Hexagon] Adding dealloc_return encoding and absolute address stores.

2015-01-06 16:15:15 +00:00

pred-gp.ll

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pred-instrs.ll

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predicate-copy.ll

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remove_lsr.ll

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simpletailcall.ll

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split-const32-const64.ll

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static.ll

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struct_args_large.ll

[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.

2014-12-29 20:44:51 +00:00

struct_args.ll

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sube.ll

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tail-call-trunc.ll

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tfr-to-combine.ll

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union-1.ll

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vaddh.ll

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validate-offset.ll

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zextloadi1.ll

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