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llvm-6502/test/CodeGen/R600
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Matt Arsenault 7fa80b45eb R600/SI: Fix bitcast between v2i32 and f64 
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 19:31:13 +00:00
..
32-bit-local-address-space.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
64bit-kernel-args.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
128bit-kernel-args.ll
…
add_i64.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
add.ll
R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
2014-05-15 14:41:54 +00:00
address-space.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
and.ll
R600: Add more and testcases
2014-06-09 08:36:53 +00:00
anyext.ll
R600/SI: Add a pattern for i32 anyext
2014-02-13 23:34:13 +00:00
array-ptr-calc-i32.ll
R600/SI: Fix verifier error with pseudo store instructions.
2014-05-01 16:37:52 +00:00
array-ptr-calc-i64.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
atomic_cmp_swap_local.ll
R600/SI: Add common 64-bit LDS atomics
2014-06-11 18:08:54 +00:00
atomic_load_add.ll
R600/SI: Fix backwards names for local atomic instructions.
2014-06-11 18:08:37 +00:00
atomic_load_sub.ll
R600/SI: Fix backwards names for local atomic instructions.
2014-06-11 18:08:37 +00:00
basic-branch.ll
R600: Add failing control flow tests.
2014-03-01 21:45:41 +00:00
basic-loop.ll
R600: Add failing control flow tests.
2014-03-01 21:45:41 +00:00
bfe_uint.ll
R600: Disable the BFE pattern
2014-01-23 18:49:33 +00:00
bfi_int.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
big_alu.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
bitcast.ll
R600/SI: Fix bitcast between v2i32 and f64
2014-06-11 19:31:13 +00:00
bswap.ll
R600: Fix selection failure for vector bswap
2014-06-09 16:20:25 +00:00
build_vector.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
call_fs.ll
…
call.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
cayman-loop-bug.ll
R600: Workaround for cayman loop bug
2013-12-02 17:29:37 +00:00
cf_end.ll
…
cf-stack-bug.ll
R600: Recommit 199842: Add work-around for the CF stack entry HW bug
2014-01-23 16:18:02 +00:00
codegen-prepare-addrmode-sext.ll
[CodeGenPrepare] Fix the check of the legality of an instruction.
2014-02-22 01:06:41 +00:00
combine_vloads.ll
Add target hook to prevent folding some bitcasted loads.
2013-11-15 04:42:23 +00:00
complex-folding.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
ctpop64.ll
R600/SI: Implement i64 ctpop
2014-06-10 19:18:24 +00:00
ctpop.ll
R600: Use BCNT_INT for evergreen
2014-06-10 19:18:28 +00:00
cvt_f32_ubyte.ll
R600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 17:50:44 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
…
disconnected-predset-break-bug.ll
…
dot4-folding.ll
…
elf.ll
…
elf.r600.ll
R600: Refactor stack size calculation
2014-01-22 21:55:43 +00:00
extload.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
extract_vector_elt_i16.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
fabs.ll
R600/SI: Fold fabs/fneg into src input modifier
2014-05-10 19:18:39 +00:00
fadd64.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fadd.ll
R600/SI: Expand all v8[if]32 operations
2014-02-13 23:34:15 +00:00
fceil.ll
R600/SI - Add new CI arithmetic instructions.
2014-02-24 21:01:28 +00:00
fcmp64.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.ll
…
fconst64.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
fcopysign.f32.ll
R600: Handle fcopysign
2014-06-10 19:00:20 +00:00
fcopysign.f64.ll
R600: Handle fcopysign
2014-06-10 19:00:20 +00:00
fdiv64.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fdiv.ll
…
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
ffloor.ll
R600/SI - Add new CI arithmetic instructions.
2014-02-24 21:01:28 +00:00
floor.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
fma.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fmad.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
fmax.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
fmin.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
fmul64.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fmul.ll
…
fmuladd.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fneg-fabs.ll
R600/SI: Fix fneg for 0.0
2014-02-04 07:12:38 +00:00
fneg.ll
R600/SI: Fold fabs/fneg into src input modifier
2014-05-10 19:18:39 +00:00
fp64_to_sint.ll
…
fp_to_sint.ll
…
fp_to_uint.f64.ll
R600/SI: Match fp_to_uint / uint_to_fp for f64
2014-05-22 03:20:30 +00:00
fp_to_uint.ll
…
fpext.ll
…
fptrunc.ll
…
fsqrt.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fsub64.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
fsub.ll
…
ftrunc.ll
R600/SI - Add new CI arithmetic instructions.
2014-02-24 21:01:28 +00:00
gep-address-space.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
gv-const-addrspace-fail.ll
R600: Partially fix constant initializers for structs and vectors.
2014-05-21 22:42:42 +00:00
gv-const-addrspace.ll
Allow aliases to be unnamed_addr.
2014-06-06 01:20:28 +00:00
i8-to-double-to-float.ll
…
icmp64.ll
R600/SI: Add i64 cmp tests
2013-12-10 21:11:55 +00:00
icmp-select-sete-reverse-args.ll
…
imm.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
indirect-addressing-si.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
indirect-private-64.ll
R600/SI: Fix 64-bit private loads.
2014-03-24 17:50:46 +00:00
infinite-loop-evergreen.ll
R600: Add failing control flow tests.
2014-03-01 21:45:41 +00:00
infinite-loop.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
insert_vector_elt_f64.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
insert_vector_elt.ll
R600/SI: Fix verifier error with pseudo store instructions.
2014-05-01 16:37:52 +00:00
jump-address.ll
Add a RequireStructuredCFG Field to TargetMachine.
2013-12-07 01:49:19 +00:00
kcache-fold.ll
…
kernel-args.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
lds-oqap-crash.ll
R600: LDS instructions shouldn't implicitly define OQAP
2014-03-13 17:13:04 +00:00
lds-output-queue.ll
Allow aliases to be unnamed_addr.
2014-06-06 01:20:28 +00:00
lds-size.ll
Allow aliases to be unnamed_addr.
2014-06-06 01:20:28 +00:00
legalizedag-bug-expand-setcc.ll
…
lit.local.cfg
Reduce verbiage of lit.local.cfg files
2014-06-09 22:42:55 +00:00
literals.ll
…
llvm.AMDGPU.barrier.local.ll
…
llvm.AMDGPU.bfe.i32.ll
R600: Try to convert BFE back to standard bit ops when possible.
2014-05-22 18:09:12 +00:00
llvm.AMDGPU.bfe.u32.ll
R600: Try to convert BFE back to standard bit ops when possible.
2014-05-22 18:09:12 +00:00
llvm.AMDGPU.bfi.ll
R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
2014-03-31 18:21:18 +00:00
llvm.AMDGPU.bfm.ll
R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
2014-03-31 18:21:18 +00:00
llvm.AMDGPU.cube.ll
…
llvm.AMDGPU.cvt_f32_ubyte.ll
R600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 17:50:44 +00:00
llvm.AMDGPU.imad24.ll
R600: Expand mad24 for GPUs without it
2014-05-22 18:00:20 +00:00
llvm.AMDGPU.imax.ll
R600/SI: Move instruction patterns to scalar versions.
2014-03-21 18:01:18 +00:00
llvm.AMDGPU.imin.ll
R600/SI: Move instruction patterns to scalar versions.
2014-03-21 18:01:18 +00:00
llvm.AMDGPU.imul24.ll
R600: Expand mul24 for GPUs without it
2014-05-22 18:00:24 +00:00
llvm.AMDGPU.kill.ll
R600/SI: Optimize SI_KILL for constant operands
2014-02-27 01:47:09 +00:00
llvm.AMDGPU.mul.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
llvm.AMDGPU.tex.ll
…
llvm.AMDGPU.trunc.ll
…
llvm.AMDGPU.umad24.ll
R600: Expand mad24 for GPUs without it
2014-05-22 18:00:20 +00:00
llvm.AMDGPU.umax.ll
R600: Compute masked bits for min and max
2014-03-31 19:35:33 +00:00
llvm.AMDGPU.umin.ll
R600: Compute masked bits for min and max
2014-03-31 19:35:33 +00:00
llvm.AMDGPU.umul24.ll
R600: Expand mul24 for GPUs without it
2014-05-22 18:00:24 +00:00
llvm.cos.ll
R600: Expand vector sin and cos.
2014-05-02 15:41:47 +00:00
llvm.exp2.ll
R600: Fix input modifiers lost for Cayman
2013-12-10 14:43:27 +00:00
llvm.floor.ll
…
llvm.pow.ll
R600: Enable vector fpow.
2014-02-04 17:18:37 +00:00
llvm.rint.f64.ll
R600/SI: f64 frint is legal on CI
2014-04-17 17:06:37 +00:00
llvm.rint.ll
R600/SI: f64 frint is legal on CI
2014-04-17 17:06:37 +00:00
llvm.round.ll
R600: Add support for ISD::FROUND
2013-11-27 21:23:20 +00:00
llvm.SI.fs.interp.constant.ll
…
llvm.SI.imageload.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
llvm.SI.load.dword.ll
R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
2014-01-27 07:20:51 +00:00
llvm.SI.resinfo.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
llvm.SI.sample-masked.ll
R600/SI: Add ShaderType attribute to some tests
2014-02-13 23:34:07 +00:00
llvm.SI.sample.ll
R600/SI: Add ShaderType attribute to some tests
2014-02-13 23:34:07 +00:00
llvm.SI.sampled.ll
R600/SI: Add ShaderType attribute to some tests
2014-02-13 23:34:07 +00:00
llvm.SI.sendmsg.ll
R600/SI: Add intrinsic for S_SENDMSG instruction
2014-01-27 07:20:44 +00:00
llvm.SI.tbuffer.store.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
llvm.SI.tid.ll
…
llvm.sin.ll
R600: Expand vector sin and cos.
2014-05-02 15:41:47 +00:00
llvm.sqrt.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
llvm.trunc.ll
R600: Allow ftrunc
2013-12-20 05:11:55 +00:00
load64.ll
R600/SI: Minor improvements to test.
2013-12-14 00:38:04 +00:00
load-i1.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
load-input-fold.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
load.ll
R600/SI: Split global vector loads with more than 4 elements
2014-02-13 23:34:10 +00:00
load.vec.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
local-64.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
local-atomics64.ll
R600/SI: Add common 64-bit LDS atomics
2014-06-11 18:08:54 +00:00
local-atomics.ll
R600/SI: Use LDS atomic inc / dec
2014-06-11 18:08:45 +00:00
local-memory-two-objects.ll
Allow aliases to be unnamed_addr.
2014-06-06 01:20:28 +00:00
local-memory.ll
Allow aliases to be unnamed_addr.
2014-06-06 01:20:28 +00:00
loop-address.ll
…
loop-idiom.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
lshl.ll
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
lshr.ll
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
mad_int24.ll
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
mad_uint24.ll
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
max-literals.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
mubuf.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
mul_int24.ll
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
mul_uint24.ll
SelectionDAG: Use helper function to improve legalization of ISD::MUL
2014-04-11 16:12:01 +00:00
mul.ll
R600: Fix test. Using wrong check prefix.
2014-06-05 08:00:36 +00:00
mulhu.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
or.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
packetizer.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
predicate-dp4.ll
R600: Make dot_4 instructions predicable
2013-11-16 16:24:41 +00:00
predicates.ll
R600: Enable the IR structurizer by default
2013-11-18 19:43:44 +00:00
private-memory.ll
R600/SI: Fix verifier error with pseudo store instructions.
2014-05-01 16:37:52 +00:00
pv-packing.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
pv.ll
R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
2014-05-09 16:42:16 +00:00
r600-encoding.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
r600-export-fix.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
R600: Fix an infinite loop when trying to reorganize export/tex vector input
2013-12-10 14:43:31 +00:00
r600cfg.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
README
…
reciprocal.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
register-count-comments.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
rotr.ll
R600/SI: Move patterns to match add / sub to scalar instructions
2013-11-18 20:09:29 +00:00
rsq.ll
R600/SI: Match rsq instructions
2014-06-05 00:15:55 +00:00
rv7x0_count3.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
salu-to-valu.ll
R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions
2014-05-09 16:42:22 +00:00
scalar_to_vector.ll
R600/SI: Fix selection failure on scalar_to_vector
2014-06-11 17:40:32 +00:00
schedule-fs-loop-nested-if.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-vs-if-nested-loop-failure.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
schedule-vs-if-nested-loop.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
sdiv.ll
…
select64.ll
R600/SI: Lower i64 SELECT by bitcasting to a vector type
2014-03-31 14:01:55 +00:00
select-vectors.ll
R600/SI: Expand selects on vectors.
2014-03-06 17:34:03 +00:00
select.ll
…
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
…
selectcc.ll
R600: Expand i64 SELECT_CC
2014-05-09 16:42:19 +00:00
set-dx10.ll
…
setcc64.ll
R600/SI: Use VALU instructions for i1 ops
2014-05-15 14:41:50 +00:00
setcc-equivalent.ll
Fix missing RUN line in test
2014-04-01 18:34:13 +00:00
setcc.ll
R600/SI: Use VALU instructions for i1 ops
2014-05-15 14:41:50 +00:00
seto.ll
R600/SI: Prettier display of input modifiers
2014-05-10 19:18:33 +00:00
setuo.ll
R600/SI: Prettier display of input modifiers
2014-05-10 19:18:33 +00:00
sext-in-reg.ll
R600: Try to convert BFE back to standard bit ops when possible.
2014-05-22 18:09:12 +00:00
sgpr-control-flow.ll
R600/SI: Only select SALU instructions in the entry or exit block
2014-04-29 23:12:48 +00:00
sgpr-copy-duplicate-operand.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
sgpr-copy.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
shared-op-cycle.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
shl.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
si-annotate-cf-assertion.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
si-lod-bias.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
si-sgpr-spill.ll
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
si-vector-hang.ll
…
sign_extend.ll
R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
2014-06-10 18:54:59 +00:00
simplify-demanded-bits-build-pair.ll
Make SimplifyDemandedBits understand BUILD_PAIR
2014-05-12 17:14:48 +00:00
sint_to_fp64.ll
SelectionDAG: Expand SELECT_CC to SELECT + SETCC
2014-06-10 16:01:22 +00:00
sint_to_fp.ll
R600/SI: Fix [s|u]int_to_fp for i1
2014-05-31 06:47:42 +00:00
smrd.ll
R600/SI: Fix SMRD pattern for offsets > 32 bits
2014-05-09 16:42:21 +00:00
sra.ll
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
srl.ll
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
store-v3i32.ll
R600: Add failing testcase for <3 x i32> stores.
2014-03-25 16:50:55 +00:00
store-v3i64.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
store-vector-ptrs.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
store.ll
R600: Expand TruncStore i64 -> {i16,i8}
2014-05-02 15:41:46 +00:00
store.r600.ll
…
structurize1.ll
R600: Fix a crash in the AMDILCFGStrucurizer
2013-11-18 19:43:38 +00:00
structurize.ll
R600: Enable the IR structurizer by default
2013-11-18 19:43:44 +00:00
sub.ll
R600/SI: Keep 64-bit not on SALU
2014-06-09 16:36:31 +00:00
swizzle-export.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
tex-clause-antidep.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
texture-input-merge.ll
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
trunc-store-i1.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
trunc-vector-store-assertion-failure.ll
…
trunc.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
uaddo.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
udiv.ll
…
udivrem64.ll
R600: Try to convert BFE back to standard bit ops when possible.
2014-05-22 18:09:12 +00:00
uint_to_fp.f64.ll
SelectionDAG: Expand SELECT_CC to SELECT + SETCC
2014-06-10 16:01:22 +00:00
uint_to_fp.ll
R600/SI: Fix [s|u]int_to_fp for i1
2014-05-31 06:47:42 +00:00
unaligned-load-store.ll
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
2014-04-29 23:12:53 +00:00
unhandled-loop-condition-assertion.ll
R600: Add failing control flow tests.
2014-03-01 21:45:41 +00:00
unroll.ll
R600: Unconditionally unroll loops that contain GEPs with alloca pointers
2014-01-23 18:49:28 +00:00
unsupported-cc.ll
…
urecip.ll
…
urem.ll
…
v1i64-kernel-arg.ll
R600: Match sign_extend_inreg to BFE instructions
2014-03-17 18:58:11 +00:00
v_cndmask.ll
R600/SI: Promote f32 SELECT to i32
2014-05-16 20:56:41 +00:00
valu-i1.ll
R600/SI: Use VALU instructions for copying i1 values
2014-04-30 15:31:33 +00:00
vertex-fetch-encoding.ll
…
vselect64.ll
SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type
2013-11-22 00:41:05 +00:00
vselect.ll
…
vtx-fetch-branch.ll
R600: Correctly handle vertex fetch clauses the precede ENDIFs
2014-01-23 18:49:31 +00:00
vtx-schedule.ll
Fix broken CHECK lines.
2014-01-11 21:06:00 +00:00
wait.ll
…
work-item-intrinsics.ll
R600/SI: Print more immediates in hex format
2014-04-15 22:32:49 +00:00
wrong-transalu-pos-fix.ll
…
xor.ll
R600/SI: Keep 64-bit not on SALU
2014-06-09 16:36:31 +00:00
zero_extend.ll
R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR
2014-04-18 00:36:21 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.