llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00

History

Tom Stellard 3cae823f69 R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188598 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-16 23:51:33 +00:00
..
64bit-kernel-args.ll	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
128bit-kernel-args.ll	R600: Use KCache for kernel arguments	2013-07-23 01:48:18 +00:00
add.ll	R600: Use KCache for kernel arguments	2013-07-23 01:48:18 +00:00
and.ll	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
bfe_uint.ll
bfi_int.ll	R600/SI: Add more special cases for opcodes to ensureSRegLimit()	2013-08-06 23:08:18 +00:00
bitcast.ll	R600/SI: Allow conversion between v32i8 and v8i32	2013-08-14 22:22:09 +00:00
build_vector.ll	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
call_fs.ll
cf_end.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
elf.ll
elf.r600.ll
fabs.ll	DAGCombiner: Pass the correct type to TargetLowering::isF(Abs\|Neg)Free	2013-07-23 23:55:03 +00:00
fadd64.ll
fadd.ll	R600: Expand vector float operations for both SI and R600	2013-08-16 23:51:24 +00:00
fcmp64.ll
fcmp-cnd.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
fcmp-cnde-int-args.ll
fcmp.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
fconst64.ll
fdiv64.ll
fdiv.ll	R600: Expand vector float operations for both SI and R600	2013-08-16 23:51:24 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
floor.ll
fma.ll	R600/SI: Add FMA pattern	2013-08-10 10:38:47 +00:00
fmad.ll
fmax.ll
fmin.ll
fmul64.ll
fmul.ll	R600: Expand vector float operations for both SI and R600	2013-08-16 23:51:24 +00:00
fmul.v4f32.ll	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
fmuladd.ll	R600/SI: FMA is faster than fmul and fadd for f64	2013-08-10 10:38:54 +00:00
fneg.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
fp64_to_sint.ll	R600/SI: Implement sint<->fp64 conversions	2013-08-08 16:06:08 +00:00
fp_to_sint.ll	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
fp_to_uint.ll	R600/SI: Add pattern for fp_to_uint	2013-08-14 22:21:57 +00:00
fpext.ll	R600/SI: Implement fp32<->fp64 conversions	2013-08-08 16:06:15 +00:00
fptrunc.ll	R600/SI: Implement fp32<->fp64 conversions	2013-08-08 16:06:15 +00:00
fsqrt.ll
fsub64.ll
fsub.ll	R600: Expand vector float operations for both SI and R600	2013-08-16 23:51:24 +00:00
i8-to-double-to-float.ll	R600: Use KCache for kernel arguments	2013-07-23 01:48:18 +00:00
icmp-select-sete-reverse-args.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
imm.ll
indirect-addressing-si.ll	R600/SI: Add missing test for r187749	2013-08-05 22:45:56 +00:00
indirect-addressing.ll
jump-address.ll	R600: Don't emit empty then clause and use alu_pop_after	2013-07-19 21:45:15 +00:00
kcache-fold.ll	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
legalizedag-bug-expand-setcc.ll
lit.local.cfg	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
literals.ll	R600: Enable folding of inline literals into REQ_SEQUENCE instructions	2013-08-16 01:11:55 +00:00
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.cube.ll
llvm.AMDGPU.imax.ll
llvm.AMDGPU.imin.ll
llvm.AMDGPU.mul.ll
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trunc.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
llvm.AMDGPU.umax.ll
llvm.AMDGPU.umin.ll
llvm.cos.ll
llvm.floor.ll	R600: Expand vector FFLOOR ops	2013-08-16 23:51:29 +00:00
llvm.pow.ll
llvm.rint.ll	R600: Expand vector FRINT ops	2013-08-16 23:51:33 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll	R600/SI: Use i8 types for resource descriptors in tests	2013-08-14 23:24:37 +00:00
llvm.SI.resinfo.ll	R600/SI: Use i8 types for resource descriptors in tests	2013-08-14 23:24:37 +00:00
llvm.SI.sample.ll	R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics	2013-08-14 23:24:53 +00:00
llvm.SI.sampled.ll	R600/SI: Convert v16i8 resource descriptors to i128	2013-08-14 23:24:45 +00:00
llvm.SI.tid.ll
llvm.sin.ll
load64.ll
load-input-fold.ll
load.ll	R600: Add support for global vector loads with element types less than 32-bits	2013-08-16 01:12:16 +00:00
load.vec.ll	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
local-memory-two-objects.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
local-memory.ll	R600/SI: Fix broken encoding of DS_WRITE_B32	2013-08-16 16:19:24 +00:00
loop-address.ll	R600: Use KCache for kernel arguments	2013-07-23 01:48:18 +00:00
lshl.ll	R600/SI: Add more special cases for opcodes to ensureSRegLimit()	2013-08-06 23:08:18 +00:00
lshr.ll	R600/SI: Add more special cases for opcodes to ensureSRegLimit()	2013-08-06 23:08:18 +00:00
mad_int24.ll	R600: Add support for 24-bit MAD instructions	2013-07-23 01:48:49 +00:00
mad_uint24.ll	R600: Add support for 24-bit MAD instructions	2013-07-23 01:48:49 +00:00
max-literals.ll	R600: Avoid more than 4 literals in the same instruction group at scheduling	2013-07-31 19:32:07 +00:00
mul_int24.ll	R600: Add support for 24-bit MUL instructions	2013-07-23 01:48:42 +00:00
mul_uint24.ll	R600: Add support for 24-bit MUL instructions	2013-07-23 01:48:42 +00:00
mul.ll
mulhu.ll
or.ll
packetizer.ll
parallelandifcollapse.ll	Factor FlattenCFG out from SimplifyCFG	2013-08-06 02:43:45 +00:00
parallelorifcollapse.ll	Factor FlattenCFG out from SimplifyCFG	2013-08-06 02:43:45 +00:00
predicates.ll
pv-packing.ll
pv.ll
r600-encoding.ll
r600cfg.ll	R600: Don't emit empty then clause and use alu_pop_after	2013-07-19 21:45:15 +00:00
README
reciprocal.ll
rotr.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
rv7x0_count3.ll
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
selectcc-cnd.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
selectcc-cnde-int.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
selectcc-icmp-select-float.ll
selectcc-opt.ll	R600: Use KCache for kernel arguments	2013-07-23 01:48:18 +00:00
set-dx10.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
setcc.ll	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
seto.ll
setuo.ll
sgpr-copy.ll	R600/SI: Use VSrc_* register classes as the default classes for types	2013-08-06 23:08:28 +00:00
shl.ll
short-args.ll	R600: Improve support for < 32-bit loads	2013-07-23 01:48:35 +00:00
si-lod-bias.ll	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	2013-08-14 23:24:32 +00:00
si-vector-hang.ll	R600: Add support for i16 and i8 global stores	2013-08-16 01:12:06 +00:00
sign_extend.ll
sint_to_fp64.ll	R600/SI: Implement sint<->fp64 conversions	2013-08-08 16:06:08 +00:00
sint_to_fp.ll	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
sra.ll
srl.ll
store.ll	R600: Add support for global vector stores with elements less than 32-bits	2013-08-16 01:12:11 +00:00
store.r600.ll	R600: Change the RAT instruction assembly names so they match the docs	2013-08-16 01:11:46 +00:00
sub.ll	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
swizzle-export.ll	[R600] Replicate old DAGCombiner behavior in target specific DAG combine.	2013-07-30 00:27:16 +00:00
tex-clause-antidep.ll
texture-input-merge.ll
udiv.ll
uint_to_fp.ll	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
unsupported-cc.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
urecip.ll
urem.ll
vertex-fetch-encoding.ll	R600: Add support for v4i32 stores on Cayman	2013-08-16 01:12:00 +00:00
vselect.ll	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
vtx-schedule.ll	R600: Use KCache for kernel arguments	2013-07-23 01:48:18 +00:00
work-item-intrinsics.ll	R600: Change the RAT instruction assembly names so they match the docs	2013-08-16 01:11:46 +00:00
xor.ll	R600/SI: Add pattern for xor of i1	2013-08-16 16:19:31 +00:00
zero_extend.ll	R600: Change the RAT instruction assembly names so they match the docs	2013-08-16 01:11:46 +00:00

README

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.