llvm-6502/lib/CodeGen
Ken Dyck bceddbdc91 Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() in
LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple
type by one, getHalfSizedIntegerVT() searches for the smallest simple integer
type that is at least half the size of the type it is called on. This approach
has the advantage that it will continue working if a new value type (such as
i24) is added to MVT.

Also, in preparation for new value types, remove the assertions that
non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and
truncstore operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17 20:09:43 +00:00
..
AsmPrinter Add support to emit debug info for C++ namespaces. 2009-12-15 19:16:48 +00:00
PBQP Mark more constants unsigned, as warned about by icc (#68). 2009-09-06 12:56:52 +00:00
SelectionDAG Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() in 2009-12-17 20:09:43 +00:00
AggressiveAntiDepBreaker.cpp <rdar://problem/7453528>. Track only physical registers that are valid for the target. 2009-12-09 17:18:22 +00:00
AggressiveAntiDepBreaker.h <rdar://problem/7453528>. Track only physical registers that are valid for the target. 2009-12-09 17:18:22 +00:00
AntiDepBreaker.h Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. 2009-11-20 19:32:48 +00:00
BranchFolding.cpp Initialize uninitialized variables. 2009-12-16 00:01:27 +00:00
BranchFolding.h Split tail duplication into a separate pass. This is needed to avoid 2009-11-26 00:32:21 +00:00
CalcSpillWeights.cpp Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. 2009-12-14 06:49:42 +00:00
CMakeLists.txt Added CalcSpillWeights to CMakeLists. 2009-12-14 07:43:25 +00:00
CodePlacementOpt.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
CriticalAntiDepBreaker.cpp <rdar://problem/7453528>. Track only physical registers that are valid for the target. 2009-12-09 17:18:22 +00:00
CriticalAntiDepBreaker.h Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. 2009-11-20 19:32:48 +00:00
DeadMachineInstructionElim.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
DwarfEHPrepare.cpp Pull LLVMContext out of PromoteMemToReg. 2009-11-23 03:50:44 +00:00
ELF.h Move DataTypes.h to include/llvm/System, update all users. This breaks the last 2009-10-26 01:35:46 +00:00
ELFCodeEmitter.cpp Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
ELFCodeEmitter.h Change ELFCodeEmitter logic to emit the constant pool and jump tables to 2009-07-21 23:13:26 +00:00
ELFWriter.cpp strength reduce a ton of type equality tests to check the typeid (Through 2009-10-05 05:54:46 +00:00
ELFWriter.h Implement the JIT side of the GDB JIT debugging interface. To enable this 2009-09-20 23:52:43 +00:00
ExactHazardRecognizer.cpp Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. 2009-11-03 20:57:50 +00:00
ExactHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
GCMetadata.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
GCMetadataPrinter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
GCStrategy.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
IfConversion.cpp Allow target to disable if-converting predicable instructions. e.g. NEON instructions under ARM mode. 2009-11-21 06:20:26 +00:00
IntrinsicLowering.cpp Codegen support for the llvm.invariant/lifetime.start/end intrinsics: 2009-11-10 09:08:09 +00:00
LatencyPriorityQueue.cpp Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. 2009-11-20 19:32:48 +00:00
LiveInterval.cpp Added a new "splitting" spiller. 2009-12-09 05:39:12 +00:00
LiveIntervalAnalysis.cpp Reuse lowered phi nodes. 2009-12-16 18:55:53 +00:00
LiveStackAnalysis.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
LiveVariables.cpp Move PHIElimination::isLiveOut method to LiveVariables. 2009-12-01 17:13:31 +00:00
LLVMTargetMachine.cpp Remove debugging code. 2009-12-17 18:03:12 +00:00
LowerSubregs.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
MachineBasicBlock.cpp Helpful comment added. Some code cleanup. No functional change. 2009-12-16 00:08:36 +00:00
MachineDominators.cpp Explicit template instantiations must happen in the template's immediately 2009-12-16 00:13:24 +00:00
MachineFunction.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
MachineFunctionAnalysis.cpp Constify MachineFunctionAnalysis' TargetMachine reference. 2009-11-09 18:18:49 +00:00
MachineFunctionPass.cpp Add a form of addPreserved which takes a string argument, to allow passes 2009-10-08 17:00:02 +00:00
MachineInstr.cpp Add @earlyclobber TableGen constraint 2009-12-16 19:43:02 +00:00
MachineLICM.cpp Enable hoisting load from constant memories. 2009-11-20 23:31:34 +00:00
MachineLoopInfo.cpp Explicit template instantiations must happen in the template's immediately 2009-12-16 00:13:24 +00:00
MachineModuleInfo.cpp Remove DebugLabelFolder pass. It is not used by dwarf writer anymore. 2009-11-24 19:37:07 +00:00
MachineModuleInfoImpls.cpp Don't sort the vector when it is empty. This should fix some expensive checking 2009-09-16 11:43:12 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Simplify a few more uses of reg_iterator. 2009-09-25 22:26:13 +00:00
MachineSink.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
MachineSSAUpdater.cpp Watch out for duplicated PHI instructions. 2009-12-07 23:11:03 +00:00
MachineVerifier.cpp Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of 2009-12-05 00:44:40 +00:00
MachO.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOCodeEmitter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOCodeEmitter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOWriter.cpp eliminate the "Value" printing methods that print to a std::ostream. 2009-08-23 04:37:46 +00:00
MachOWriter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
Makefile
MaxStackAlignment.cpp Factor the stack alignment calculations out into a target independent pass. 2009-12-02 19:30:24 +00:00
ObjectCodeEmitter.cpp Remove accidental commited comment 2009-08-05 07:00:43 +00:00
OcamlGC.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
Passes.cpp
PHIElimination.cpp Reuse lowered phi nodes. 2009-12-16 18:55:53 +00:00
PHIElimination.h Reuse lowered phi nodes. 2009-12-16 18:55:53 +00:00
PostRASchedulerList.cpp <rdar://problem/7453528>. Track only physical registers that are valid for the target. 2009-12-09 17:18:22 +00:00
PreAllocSplitting.cpp Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. 2009-12-14 06:49:42 +00:00
ProcessImplicitDefs.cpp When all defs of a vr are implicit_def, delete all of the defs. 2009-11-26 00:32:36 +00:00
PrologEpilogInserter.cpp Honour setHasCalls() set from isel. 2009-12-11 19:39:55 +00:00
PrologEpilogInserter.h Re-enable register scavenging in Thumb1 by default. 2009-10-08 01:46:59 +00:00
PseudoSourceValue.cpp Do some cleanups suggested by Chris. 2009-11-12 21:49:55 +00:00
README.txt This remat entry is basically done. There are hooks to allow targets 2009-10-14 00:02:01 +00:00
RegAllocLinearScan.cpp Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. 2009-12-14 06:49:42 +00:00
RegAllocLocal.cpp Do better with physical reg operands (typically, from inline asm) 2009-12-16 00:29:41 +00:00
RegAllocPBQP.cpp Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. 2009-12-14 06:49:42 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
ScheduleDAG.cpp Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. 2009-11-20 19:32:48 +00:00
ScheduleDAGEmit.cpp Add assertion checks here to turn silent miscompiles into aborts. 2009-10-30 23:59:06 +00:00
ScheduleDAGInstrs.cpp Fix dependencies added to model memory aliasing for post-RA scheduling. The dependencies were overly conservative for memory access that are known not to alias. 2009-11-09 19:22:17 +00:00
ScheduleDAGInstrs.h Spill slots cannot alias. 2009-10-18 19:58:47 +00:00
ScheduleDAGPrinter.cpp Remove ShortNames from getNodeLabel in DOTGraphTraits 2009-11-30 12:38:47 +00:00
ShadowStackGC.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
ShrinkWrapping.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:46:59 +00:00
SimpleHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
SimpleRegisterCoalescing.cpp Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. 2009-12-14 06:49:42 +00:00
SimpleRegisterCoalescing.h Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. 2009-12-14 06:49:42 +00:00
SjLjEHPrepare.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
SlotIndexes.cpp Added an API to the SlotIndexes pass to allow new instructions to be inserted into the numbering. 2009-11-14 00:02:51 +00:00
Spiller.cpp Added a new "splitting" spiller. 2009-12-09 05:39:12 +00:00
Spiller.h Added a new "splitting" spiller. 2009-12-09 05:39:12 +00:00
StackProtector.cpp Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 2009-10-25 06:33:48 +00:00
StackSlotColoring.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
StrongPHIElimination.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
TailDuplication.cpp Tail duplication should zap a copy it inserted for SSA update if the copy is the only use of its source. 2009-12-15 01:44:10 +00:00
TargetInstrInfoImpl.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
TwoAddressInstructionPass.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
UnreachableBlockElim.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
VirtRegMap.cpp Add a bool flag to StackObjects telling whether they reference spill 2009-11-12 20:49:22 +00:00
VirtRegMap.h The Indexes Patch. 2009-11-03 23:52:08 +00:00
VirtRegRewriter.cpp improve portability to avoid conflicting with std::next in c++'0x. 2009-12-03 00:50:42 +00:00
VirtRegRewriter.h Kill off more cerr/cout uses and prune includes a bit. 2009-08-23 11:37:21 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.