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bd5f9f45d1
llvm-6502/lib/Target/R600
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Matt Arsenault bd5f9f45d1 R600/SI: Fix suspicious indexing 
The loop is over the operands of an instruction, and checks the
register with the sub reg index of the dest register. This probably
meant to be checking the sub reg index of the same operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-03 05:22:32 +00:00
..
AsmParser R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
InstPrinter R600/SI: Change mubuf offsets to print as decimal 2014-12-03 03:12:13 +00:00
MCTargetDesc R600: Fix assert on empty function 2014-11-13 20:07:40 +00:00
TargetInfo
AMDGPU.h R600/SI: Add SIFoldOperands pass 2014-11-21 22:06:37 +00:00
AMDGPU.td R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
AMDGPUAlwaysInlinePass.cpp Reapply: R600: Make sure to inline all internal functions 2014-11-03 19:49:05 +00:00
AMDGPUAsmPrinter.cpp R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
AMDGPUAsmPrinter.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp R600: Remove dead code 2014-10-07 21:29:56 +00:00
AMDGPUInstrInfo.h R600: Remove dead code 2014-10-07 21:29:56 +00:00
AMDGPUInstrInfo.td R600/SI: Combine min3/max3 instructions 2014-11-14 20:08:52 +00:00
AMDGPUInstructions.td R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime 2014-12-02 17:05:41 +00:00
AMDGPUISelLowering.cpp R600/SI: Use ZeroOrNegativeOneBooleanContent 2014-11-26 21:23:15 +00:00
AMDGPUISelLowering.h R600: Factor i64 UDIVREM lowering into its own fuction 2014-11-15 01:07:53 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h Reapply "R600: Add new intrinsic to read work dimensions" 2014-10-14 20:05:26 +00:00
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp R600: Don't promote allocas when one of the users is a ptrtoint instruction 2014-10-31 20:52:04 +00:00
AMDGPURegisterInfo.cpp R600/SI: Enable inline assembly 2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
AMDGPUSubtarget.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
AMDGPUTargetMachine.cpp R600/SI: Fix running SILowerI1Copies a second time 2014-12-03 05:22:30 +00:00
AMDGPUTargetMachine.h This patch changes the ownership of TLOF from TargetLoweringBase to TargetMachine so that different subtargets could share the TLOF effectively 2014-11-13 09:26:31 +00:00
AMDGPUTargetTransformInfo.cpp Fix broken doxygen annotations, NFC 2014-11-12 18:25:06 +00:00
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
CaymanInstructions.td
CMakeLists.txt R600/SI: Add SIFoldOperands pass 2014-11-21 22:06:37 +00:00
EvergreenInstructions.td R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs 2014-11-02 23:46:54 +00:00
LLVMBuild.txt R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
Makefile R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp Remove unnecessary copying or replace it with moves in a bunch of places. 2014-10-04 16:55:56 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
R600InstrInfo.cpp Remove unused argument to CreateTargetScheduleState and change 2014-10-09 01:59:35 +00:00
R600InstrInfo.h Remove unused argument to CreateTargetScheduleState and change 2014-10-09 01:59:35 +00:00
R600Instructions.td Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. 2014-11-26 00:46:26 +00:00
R600Intrinsics.td
R600ISelLowering.cpp R600/SI: Use ZeroOrNegativeOneBooleanContent 2014-11-26 21:23:15 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp Eliminate some deep std::vector copies. NFC. 2014-10-03 18:33:16 +00:00
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h R600/SI: Move more information into SIProgramInfo struct 2014-12-02 21:28:53 +00:00
SIFixSGPRCopies.cpp R600/SI: Fix suspicious indexing 2014-12-03 05:22:32 +00:00
SIFixSGPRLiveRanges.cpp R600/SI: Fix the FixSGPRLiveRanges pass 2014-09-24 01:33:24 +00:00
SIFoldOperands.cpp R600/SI: Add SIFoldOperands pass 2014-11-21 22:06:37 +00:00
SIInsertWaits.cpp Fix include order 2014-09-29 15:53:15 +00:00
SIInstrFormats.td R600/SI: Various instruction format bit test cleanups 2014-12-01 15:52:46 +00:00
SIInstrInfo.cpp R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime 2014-12-02 17:05:41 +00:00
SIInstrInfo.h R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime 2014-12-02 17:05:41 +00:00
SIInstrInfo.td R600/SI: Various instruction format bit test cleanups 2014-12-01 15:52:46 +00:00
SIInstructions.td Revert r222746: That commit did not update any tests and caused two R600 2014-11-25 10:50:41 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600/SI: Set correct number of user sgprs for HSA runtime 2014-12-02 17:41:43 +00:00
SIISelLowering.h R600/SI: Combine min3/max3 instructions 2014-11-14 20:08:52 +00:00
SILoadStoreOptimizer.cpp R600/SI: Fix live range error hidden by SIFoldOperands 2014-12-03 05:22:29 +00:00
SILowerControlFlow.cpp Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime. 2014-11-24 14:03:16 +00:00
SILowerI1Copies.cpp R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies 2014-11-26 18:18:28 +00:00
SIMachineFunctionInfo.cpp R600/SI: Implement VGPR register spilling for compute at -O0 v3 2014-09-24 01:33:17 +00:00
SIMachineFunctionInfo.h R600/SI: Implement VGPR register spilling for compute at -O0 v3 2014-09-24 01:33:17 +00:00
SIRegisterInfo.cpp R600/SI: Fix allocating flat_scr_lo / flat_scr_hi 2014-11-25 07:53:06 +00:00
SIRegisterInfo.h R600/SI: Add new helper isSGPRClassID 2014-09-24 02:17:12 +00:00
SIRegisterInfo.td R600/SI: Fix assembly names for exec_hi and exec_lo 2014-11-14 14:08:04 +00:00
SISchedule.td
SIShrinkInstructions.cpp R600/SI: Use s_movk_i32 2014-11-13 20:44:23 +00:00
SITypeRewriter.cpp Revert "IR: MDNode => Value" 2014-11-11 21:30:22 +00:00