llvm-6502/lib/CodeGen
2009-10-23 23:09:19 +00:00
..
AsmPrinter Tidying up some code and comments. No functionality change. 2009-10-22 20:48:59 +00:00
PBQP Mark more constants unsigned, as warned about by icc (#68). 2009-09-06 12:56:52 +00:00
SelectionDAG APInt-ify the gep scaling code, so that it correctly handles the case where 2009-10-23 17:57:43 +00:00
BranchFolding.cpp Revert the main portion of r31856. It was causing BranchFolding 2009-10-22 00:03:58 +00:00
BranchFolding.h Run branch folding if if-converter make some transformations. 2009-09-04 07:47:40 +00:00
CMakeLists.txt second half of lazy liveness removal. 2009-10-07 22:49:30 +00:00
CodePlacementOpt.cpp Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks are 2009-10-20 04:50:37 +00:00
DeadMachineInstructionElim.cpp Factor out LiveIntervalAnalysis' code to determine whether an instruction 2009-10-09 23:27:56 +00:00
DwarfEHPrepare.cpp Introduce and use convenience methods for getting pointer types 2009-10-06 15:40:36 +00:00
ELF.h Remove hack used to strip unwanted chars from section name 2009-08-13 21:25:27 +00:00
ELFCodeEmitter.cpp Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
ELFCodeEmitter.h Change ELFCodeEmitter logic to emit the constant pool and jump tables to 2009-07-21 23:13:26 +00:00
ELFWriter.cpp strength reduce a ton of type equality tests to check the typeid (Through 2009-10-05 05:54:46 +00:00
ELFWriter.h Implement the JIT side of the GDB JIT debugging interface. To enable this 2009-09-20 23:52:43 +00:00
ExactHazardRecognizer.cpp 80 column violation. 2009-10-16 05:18:39 +00:00
ExactHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
GCMetadata.cpp Change Pass::print to take a raw ostream instead of std::ostream, 2009-08-23 06:03:38 +00:00
GCMetadataPrinter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
GCStrategy.cpp When emitting a label for a PostCall safe point, the machine 2009-09-08 07:39:27 +00:00
IfConversion.cpp Run branch folding if if-converter make some transformations. 2009-09-04 07:47:40 +00:00
IntrinsicLowering.cpp I don't see any point in having both eh.selector.i32 and eh.selector.i64, 2009-10-14 16:11:37 +00:00
LatencyPriorityQueue.cpp Add initial support for back-scheduling address computations, 2008-12-16 03:35:01 +00:00
LiveInterval.cpp Oops. Renamed remaining MachineInstrIndex references. 2009-10-03 04:31:31 +00:00
LiveIntervalAnalysis.cpp Trim unnecessary includes. 2009-10-20 04:23:20 +00:00
LiveStackAnalysis.cpp Change Pass::print to take a raw ostream instead of std::ostream, 2009-08-23 06:03:38 +00:00
LiveVariables.cpp When LiveVariables is adding implicit-def to model "partial dead", add the earlyclobber marker if the superreg def has it. 2009-10-14 23:39:27 +00:00
LLVMTargetMachine.cpp Change createPostRAScheduler so it can be turned off at llc -O1. 2009-10-16 21:06:15 +00:00
LowerSubregs.cpp Use KILL instead of IMPLICIT_DEF in LowerSubregs pass. 2009-09-28 20:32:46 +00:00
MachineBasicBlock.cpp remove std::ostream versions of printing stuff for MBB and MF, 2009-08-23 03:13:20 +00:00
MachineDominators.cpp Change Pass::print to take a raw ostream instead of std::ostream, 2009-08-23 06:03:38 +00:00
MachineFunction.cpp Add basic infrastructure and x86 support for preserving MachineMemOperand 2009-10-09 18:10:05 +00:00
MachineFunctionAnalysis.cpp Fix PR5087, patch by Jakub Staszak! 2009-10-12 04:22:44 +00:00
MachineFunctionPass.cpp Add a form of addPreserved which takes a string argument, to allow passes 2009-10-08 17:00:02 +00:00
MachineInstr.cpp Need a comma after imp-use. 2009-10-21 07:56:02 +00:00
MachineLICM.cpp Factor out LiveIntervalAnalysis' code to determine whether an instruction 2009-10-09 23:27:56 +00:00
MachineLoopInfo.cpp Add getTopBlock and getBottomBlock member functions to MachineLoopInfo. 2009-10-20 04:16:37 +00:00
MachineModuleInfo.cpp Clear variable debug info map at the end of the function. 2009-10-08 20:41:17 +00:00
MachineModuleInfoImpls.cpp Don't sort the vector when it is empty. This should fix some expensive checking 2009-09-16 11:43:12 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Simplify a few more uses of reg_iterator. 2009-09-25 22:26:13 +00:00
MachineSink.cpp Fix a typo in a comment. 2009-10-19 14:56:05 +00:00
MachineVerifier.cpp Add a few simple MachineVerifier checks for MachineMemOperands. 2009-10-07 17:36:00 +00:00
MachO.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOCodeEmitter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOCodeEmitter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOWriter.cpp eliminate the "Value" printing methods that print to a std::ostream. 2009-08-23 04:37:46 +00:00
MachOWriter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
ObjectCodeEmitter.cpp Remove accidental commited comment 2009-08-05 07:00:43 +00:00
OcamlGC.cpp Registry.h should not depend on CommandLine.h. 2009-01-16 07:02:28 +00:00
Passes.cpp
PHIElimination.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
PHIElimination.h Fix comment for consistency sake. 2009-09-04 07:46:30 +00:00
PostRASchedulerList.cpp Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 2009-10-22 23:19:17 +00:00
PreAllocSplitting.cpp Oops. Backing out 84681 - needs to wait for the indexing patch. 2009-10-20 21:28:22 +00:00
PrologEpilogInserter.cpp Cleanup of frame index scavenging. Better code flow and more accurately 2009-10-21 15:26:21 +00:00
PrologEpilogInserter.h Re-enable register scavenging in Thumb1 by default. 2009-10-08 01:46:59 +00:00
PseudoSourceValue.cpp Spill slots cannot alias. 2009-10-18 19:58:47 +00:00
README.txt This remat entry is basically done. There are hooks to allow targets 2009-10-14 00:02:01 +00:00
RegAllocLinearScan.cpp Renamed MachineInstrIndex to LiveIndex. 2009-10-03 04:21:37 +00:00
RegAllocLocal.cpp Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. 2009-10-17 09:20:14 +00:00
RegAllocPBQP.cpp Renamed MachineInstrIndex to LiveIndex. 2009-10-03 04:21:37 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp The spill restore needs to be resolved to the SP/FP just like the spill 2009-10-21 22:59:56 +00:00
ScheduleDAG.cpp Fix integer overflow in instruction scheduling. This can happen if we have 2009-09-30 20:15:38 +00:00
ScheduleDAGEmit.cpp Improve MachineMemOperand handling. 2009-09-25 20:36:54 +00:00
ScheduleDAGInstrs.cpp Spill slots cannot alias. 2009-10-18 19:58:47 +00:00
ScheduleDAGInstrs.h Spill slots cannot alias. 2009-10-18 19:58:47 +00:00
ScheduleDAGPrinter.cpp Trim unnecessary includes. 2009-10-20 04:23:20 +00:00
ShadowStackGC.cpp Introduce and use convenience methods for getting pointer types 2009-10-06 15:40:36 +00:00
ShrinkWrapping.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:46:59 +00:00
SimpleHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
SimpleRegisterCoalescing.cpp Identity copies should not contribute to spill weight. 2009-10-23 23:09:19 +00:00
SimpleRegisterCoalescing.h Factor out LiveIntervalAnalysis' code to determine whether an instruction 2009-10-09 23:27:56 +00:00
SjLjEHPrepare.cpp I don't see any point in having both eh.selector.i32 and eh.selector.i64, 2009-10-14 16:11:37 +00:00
Spiller.cpp Oops. Renamed remaining MachineInstrIndex references. 2009-10-03 04:31:31 +00:00
Spiller.h Fix some minor MSVC compiler warnings. 2009-07-19 01:38:38 +00:00
StackProtector.cpp Neuter stack protectors by only checking character arrays. This is what GCC 2009-10-23 00:01:05 +00:00
StackSlotColoring.cpp -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 2009-10-18 18:16:27 +00:00
StrongPHIElimination.cpp Oops. Renamed remaining MachineInstrIndex references. 2009-10-03 04:31:31 +00:00
TargetInstrInfoImpl.cpp -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 2009-10-18 18:16:27 +00:00
TwoAddressInstructionPass.cpp Factor out LiveIntervalAnalysis' code to determine whether an instruction 2009-10-09 23:27:56 +00:00
UnreachableBlockElim.cpp Preserve ProfileInfo. 2009-09-09 17:53:39 +00:00
VirtRegMap.cpp Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. 2009-10-17 09:20:14 +00:00
VirtRegMap.h Renamed MachineInstrIndex to LiveIndex. 2009-10-03 04:21:37 +00:00
VirtRegRewriter.cpp Revert the kludge in 76703. I got a clean 2009-10-12 18:49:00 +00:00
VirtRegRewriter.h Kill off more cerr/cout uses and prune includes a bit. 2009-08-23 11:37:21 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.