llvm-6502/test/CodeGen/ARM
Jonathan Roelofs 3d47855394 Fix thumbv4t indirect calls
So there are a couple of issues with indirect calls on thumbv4t. First, the most
'obvious' instruction, 'blx' isn't available until v5t. And secondly, the
next-most-obvious sequence: 'mov lr, pc; bx rN' doesn't DTRT in thumb code
because the saved off pc has its thumb bit cleared, so when the callee returns
we end up in ARM mode.... yuck.

The solution is to 'bl' to a nearby landing pad with a 'bx rN' in it.

We could cut down on code size by sharing the landing pads between call sites
that are close enough, but for the moment let's do correctness first and look at
performance later.


Patch by: Iain Sandoe

http://reviews.llvm.org/D6519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223380 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-04 19:34:50 +00:00
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2006-11-10-CycleInDAG.ll
2007-01-19-InfiniteLoop.ll
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2007-05-07-tailmerge-1.ll Use FileCheck in a few tests. 2014-11-06 15:05:51 +00:00
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2009-10-16-Scope.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
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2010-04-15-ScavengerDebugValue.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
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2010-06-25-Thumb2ITInvalidIterator.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
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2010-11-15-SpillEarlyClobber.ll [RegAlloc] Remove reference to the trivial spiller in test case. 2014-11-06 19:24:18 +00:00
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2011-04-12-AlignBug.ll ARM: remove ARM/Thumb distinction for preferred alignment. 2014-10-14 22:12:17 +00:00
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adv-copy-opt.ll [ARM] Move the implementation of the target hooks related to copy-related 2014-08-22 18:05:22 +00:00
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arm32-round-conv.ll [AArch32] Add patterns for VCVT{A,N,P,M}. 2014-08-25 16:56:33 +00:00
arm32-rounding.ll [ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 2014-10-01 13:13:18 +00:00
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atomic-load-store.ll Restore "[ARM, Fix] Fix emitLeading/TrailingFence on old ARM processors" 2014-09-18 18:56:04 +00:00
atomic-op.ll ARM: allow misaligned local variables in Thumb1 mode. 2014-10-14 22:12:14 +00:00
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build-attributes.ll Emit ABI_FP_rounding attribute. 2014-12-03 08:12:26 +00:00
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carry.ll Only emit movw on ARMv6T2+ 2014-09-02 22:45:13 +00:00
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dbg.ll ARM: Add patterns for dbg 2014-08-26 12:47:26 +00:00
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debug-frame-large-stack.ll ARM: simplify test. 2014-11-14 22:45:23 +00:00
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debug-frame-vararg.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
debug-frame.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
debug-info-arg.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
debug-info-blocks.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
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invalid-target.ll Fix ARM triple parsing 2014-11-17 14:08:57 +00:00
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negative-offset.ll ARM: Negative offset support problem 2014-09-09 09:57:59 +00:00
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no-tail-call.ll [ARM] Do not perform a tail call when the caller returns several values. 2014-09-18 21:17:50 +00:00
none-macho-v4t.ll Fix thumbv4t indirect calls 2014-12-04 19:34:50 +00:00
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preferred-align.ll ARM: remove ARM/Thumb distinction for preferred alignment. 2014-10-14 22:12:17 +00:00
prefetch.ll Remove the cortex-a9-mp CPU. 2014-11-03 17:38:00 +00:00
private.ll
rbit.ll
readcyclecounter.ll
reg_sequence.ll
ret0.ll
ret_arg1.ll
ret_arg2.ll
ret_arg3.ll
ret_arg4.ll
ret_arg5.ll
ret_f32_arg2.ll
ret_f32_arg5.ll
ret_f64_arg2.ll
ret_f64_arg_reg_split.ll
ret_f64_arg_split.ll
ret_f64_arg_stack.ll
ret_i64_arg2.ll
ret_i64_arg3.ll
ret_i64_arg_split.ll
ret_i128_arg2.ll
ret_sret_vector.ll
ret_void.ll
returned-ext.ll
returned-trunc-tail-calls.ll
rev.ll
saxpy10-a9.ll
sbfx.ll
section-name.ll
section.ll
segmented-stacks-dynamic.ll
segmented-stacks.ll
select_xform.ll Fix optimisations of SELECT_CC which assumed result is boolean 2014-11-17 10:49:31 +00:00
select-imm.ll
select-undef.ll
select.ll
setcc-sentinals.ll
shifter_operand.ll
shuffle.ll
sincos.ll
sjlj-prepare-critical-edge.ll
sjljehprepare-lower-empty-struct.ll
smml.ll
smul.ll
smulw.ll [ARM] Do not select SMULW[BT] or SMLAW[BT] 2014-10-20 11:30:35 +00:00
space-directive.ll ARM: add @llvm.arm.space intrinsic for testing ConstantIslands. 2014-11-13 17:58:48 +00:00
spill-q.ll
ssp-data-layout.ll
stack_guard_remat.ll [ARM, stack protector] If supported, use armv7 instructions. 2014-10-23 04:17:05 +00:00
stack-frame.ll
stack-protector-bmovpcb_call.ll
stackpointer.ll
stm.ll
str_post.ll
str_pre-2.ll
str_pre.ll
str_trunc.ll
struct_byval_arm_t1_t2.ll
struct_byval.ll
struct-byval-frame-index.ll
sub-cmp-peephole.ll
sub.ll
subreg-remat.ll
swift-atomics.ll Fix swift-atomics testcase 2014-09-23 23:18:01 +00:00
swift-vldm.ll
sxt_rot.ll
t2-imm.ll
tail-call.ll
tail-dup.ll
tail-merge-branch-weight.ll
tail-opts.ll
taildup-branch-weight.ll
test-sharedidx.ll
this-return.ll
thread_pointer.ll
thumb1_return_sequence.ll ARM / x86_64 varargs: Don't save regparms in prologue without va_start 2014-08-22 21:59:26 +00:00
thumb1-varalloc.ll [Thumb1] Re-write emitThumbRegPlusImmediate 2014-11-17 11:18:10 +00:00
thumb2-it-block.ll
thumb2-size-opt.ll [ARM] Add Thumb-2 code size optimization regression test for LSR (register). 2014-09-11 10:45:50 +00:00
thumb_indirect_calls.ll Fix thumbv4t indirect calls 2014-12-04 19:34:50 +00:00
thumb-litpool.ll
tls1.ll
tls2.ll
tls3.ll
tls-models.ll
trap.ll
trunc_ldr.ll
truncstore-dag-combine.ll
tst_teq.ll
twoaddrinstr.ll
uint64tof64.ll
umulo-32.ll
unaligned_load_store_vector.ll
unaligned_load_store.ll
undef-sext.ll
undefined.ll
unord.ll
unsafe-fsub.ll
unwind-init.ll
uxt_rot.ll
uxtb.ll
v1-constant-fold.ll
va_arg.ll
vaba.ll
vabd.ll
vabs.ll
vadd.ll
vararg_no_start.ll ARM / x86_64 varargs: Don't save regparms in prologue without va_start 2014-08-22 21:59:26 +00:00
varargs-spill-stack-align-nacl.ll ARM: try to add extra CS-register whenever stack alignment >= 8. 2014-11-05 00:27:20 +00:00
vargs_align.ll ARM / x86_64 varargs: Don't save regparms in prologue without va_start 2014-08-22 21:59:26 +00:00
vargs.ll
vbits.ll
vbsl-constant.ll
vbsl.ll
vceq.ll
vcge.ll
vcgt.ll
vcnt.ll
vcombine.ll
vcvt_combine.ll
vcvt-cost.ll
vcvt-v8.ll
vcvt.ll
vdiv_combine.ll
vdup.ll
vector-DAGCombine.ll
vector-extend-narrow.ll
vector-promotion.ll [CodeGenPrepare] Move extractelement close to store if they can be combined. 2014-10-31 17:52:53 +00:00
vector-spilling.ll
vext.ll
vfcmp.ll
vfloatintrinsics.ll
vfp-libcalls.ll
vfp-regs-dwarf.ll Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
vfp.ll
vget_lane.ll
vhadd.ll
vhsub.ll
vicmp.ll
vld1.ll
vld2.ll
vld3.ll
vld4.ll
vlddup.ll
vldlane.ll
vldm-liveness.ll
vldm-sched-a9.ll Revert 202433 - Provide a target override for the latest regalloc heuristic 2014-10-03 12:20:53 +00:00
vminmax.ll
vminmaxnm.ll [ARM] Select VMAXNM and VMINNM regardless of operand order 2014-10-27 09:23:02 +00:00
vmla.ll
vmls.ll
vmov.ll
vmul.ll
vneg.ll
vpadal.ll
vpadd.ll
vpminmax.ll
vqadd.ll
vqdmul.ll
vqshl.ll
vqshrn.ll
vqsub.ll
vrec.ll
vrev.ll
vsel.ll
vselect_imax.ll
vshift.ll
vshiftins.ll
vshl.ll
vshll.ll
vshrn.ll
vsra.ll
vst1.ll
vst2.ll
vst3.ll
vst4.ll
vstlane.ll
vsub.ll
vtbl.ll
vtrn.ll
vuzp.ll
vzip.ll
warn-stack.ll
weak2.ll
weak.ll
widen-vmovs.ll
wrong-t2stmia-size-opt.ll ARM: don't size-reduce STMs using the LR register. 2014-09-10 12:53:28 +00:00
zero-cycle-zero.ll
zextload_demandedbits.ll