Misha Brukman d36e30e623 * Changed Bcc instructions to behave like BPcc instructions ...

* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8

2003-06-06 09:52:23 +00:00

..

InstrSched

Remove usage of noncopyable classes to clean up doxygen output.

2003-06-02 22:45:07 +00:00

InstrSelection

I have finally seen the light. The code to change the opcode must live higher in

2003-06-04 04:54:06 +00:00

LiveVar

Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()

2003-05-27 00:06:48 +00:00

ModuloScheduling

compiled with the new SchedGraphCommon

2003-06-02 17:48:56 +00:00

RegAlloc

Minor changes.

2003-05-31 07:41:54 +00:00

.cvsignore

Since there is now another derived .inc file, ignore them all.

2003-05-29 20:15:27 +00:00

EmitBytecodeToAssembly.cpp

…

MachineCodeForInstruction.h

…

MachineFunctionInfo.h

…

MachineInstrAnnot.h

Renamed a variable.

2003-05-31 07:43:41 +00:00

Makefile

Use the new -o tablegen option

2003-06-03 05:06:33 +00:00

MappingInfo.cpp

lib/CodeGen/Mapping/MappingInfo.cpp:

2003-06-04 22:07:12 +00:00

MappingInfo.h

Add file comment. Include <vector> and <string>. Update include guards

2003-06-04 22:02:47 +00:00

SparcV9_F2.td

Moved predict and annul fields to the end of each individual instruction

2003-06-05 23:33:15 +00:00

SparcV9_F3.td

Added missing directive to store the instruction name.

2003-06-05 23:35:11 +00:00

SparcV9_F4.td

Added the 4.7 instruction class and all the FMOVcc instructions in them.

2003-06-04 04:48:31 +00:00

SparcV9_Reg.td

* Broke up SparcV9.td into separate files as it was getting unmanageable

2003-05-29 03:31:43 +00:00

SparcV9.burg.in

Add support for compiling varargs functions.

2003-05-25 15:59:47 +00:00

SparcV9.td

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9AsmPrinter.cpp

Reverting previous beautification changes.

2003-05-31 07:27:17 +00:00

SparcV9CodeEmitter.cpp

Fixed a bunch of test cases in test/Regression/Jello which could not get the

2003-06-06 04:41:22 +00:00

SparcV9CodeEmitter.h

Added lazy function resolution to the JIT.

2003-06-05 20:52:06 +00:00

SparcV9Instr.def

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9InstrInfo.cpp

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9InstrSelection.cpp

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9InstrSelectionSupport.h

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9Internals.h

Extensive changes to the way code generation occurs for function

2003-05-31 07:32:01 +00:00

SparcV9PeepholeOpts.cpp

Cleaned up code layout; no functional changes.

2003-05-23 19:20:57 +00:00

SparcV9PreSelection.cpp

Minor tuning -- avoid a non-inlinable function call on every operand.

2003-06-05 21:12:56 +00:00

SparcV9PrologEpilogInserter.cpp

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9RegClassInfo.cpp

Fixed `volatile' typo.

2003-05-21 19:34:28 +00:00

SparcV9RegClassInfo.h

Added special register class containing (for now) %fsr.

2003-05-27 00:02:22 +00:00

SparcV9RegInfo.cpp

* Changed Bcc instructions to behave like BPcc instructions

2003-06-06 09:52:23 +00:00

SparcV9SchedInfo.cpp

Added entries for each of the instructions with annotations ('r' or 'i').

2003-05-27 22:33:39 +00:00

SparcV9StackSlots.cpp

…

SparcV9TargetMachine.cpp

* Removed PreSelection pass because that is now done in the JIT

2003-06-06 07:11:16 +00:00