llvm-6502/test/CodeGen/Thumb2
Evan Cheng 342e3161d9 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 01:34:54 +00:00
..
2009-07-17-CrossRegClassCopy.ll
2009-07-21-ISelBug.ll
2009-07-23-CPIslandBug.ll
2009-07-30-PEICrash.ll
2009-08-01-WrongLDRBOpc.ll
2009-08-02-CoalescerBug.ll Remove support for parsing the "type i32" syntax for defining a numbered 2011-06-19 00:03:46 +00:00
2009-08-04-CoalescerAssert.ll
2009-08-04-CoalescerBug.ll Remove support for parsing the "type i32" syntax for defining a numbered 2011-06-19 00:03:46 +00:00
2009-08-04-ScavengerAssert.ll Remove support for parsing the "type i32" syntax for defining a numbered 2011-06-19 00:03:46 +00:00
2009-08-04-SubregLoweringBug2.ll
2009-08-04-SubregLoweringBug3.ll
2009-08-04-SubregLoweringBug.ll rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which is 2011-06-18 06:05:24 +00:00
2009-08-06-SpDecBug.ll Roll r127459 back in: 2011-03-11 21:52:04 +00:00
2009-08-07-CoalescerBug.ll
2009-08-07-NeonFPBug.ll
2009-08-08-ScavengerAssert.ll
2009-08-10-ISelBug.ll
2009-08-21-PostRAKill4.ll
2009-09-01-PostRAProlog.ll
2009-09-28-ITBlockBug.ll Roll r127459 back in: 2011-03-11 21:52:04 +00:00
2009-10-15-ITBlockBranch.ll Pseudo-ize the t2LDMIA_RET instruction. 2011-06-30 18:25:42 +00:00
2009-11-01-CopyReg2RegBug.ll
2009-11-11-ScavengerAssert.ll
2009-11-13-STRDBug.ll
2009-12-01-LoopIVUsers.ll Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 2011-08-30 01:34:54 +00:00
2010-01-06-TailDuplicateLabels.ll
2010-01-19-RemovePredicates.ll
2010-02-11-phi-cycle.ll
2010-02-24-BigStack.ll
2010-03-08-addi12-ccout.ll
2010-03-15-AsmCCClobber.ll Fix Thumb and Thumb2 tests to be register allocator independent. 2011-03-31 23:31:50 +00:00
2010-04-15-DynAllocBug.ll
2010-04-26-CopyRegCrash.ll
2010-05-24-rsbs.ll
2010-06-14-NEONCoalescer.ll Fix more register allocation sensitive tests. 2011-07-08 00:24:06 +00:00
2010-06-19-ITBlockCrash.ll
2010-06-21-TailMergeBug.ll Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 2011-08-03 22:34:43 +00:00
2010-08-10-VarSizedAllocaBug.ll Fix more register and coalescing dependencies. 2011-05-04 19:02:11 +00:00
2010-11-22-EpilogueBug.ll Roll r127459 back in: 2011-03-11 21:52:04 +00:00
2010-12-03-AddSPNarrowing.ll
2011-04-21-FILoweringBug.ll In Thumb2 mode, lower frame indix references to: 2011-04-22 01:42:52 +00:00
2011-06-07-TwoAddrEarlyClobber.ll Thumb1 register to register MOV instruction is predicable. 2011-06-30 22:10:46 +00:00
bfi.ll Fix more register and coalescing dependencies. 2011-05-04 19:02:11 +00:00
bfx.ll
buildvector-crash.ll
carry.ll
cortex-fp.ll
crash.ll
cross-rc-coalescing-1.ll
cross-rc-coalescing-2.ll Roll r127459 back in: 2011-03-11 21:52:04 +00:00
dg.exp
div.ll
frameless2.ll
frameless.ll
ifcvt-neon.ll
large-stack.ll
ldr-str-imm12.ll Switch ARM to using AltOrders instead of MethodBodies. 2011-06-18 01:14:46 +00:00
lsr-deficiency.ll Fix more register allocation sensitive tests. 2011-07-08 00:24:06 +00:00
machine-licm.ll Make tBX_RET and tBX_RET_vararg predicable. 2011-07-08 21:50:04 +00:00
mul_const.ll
pic-load.ll
thumb2-adc.ll
thumb2-add2.ll
thumb2-add3.ll
thumb2-add4.ll
thumb2-add5.ll
thumb2-add6.ll
thumb2-add.ll FileCheck-ize another test. Reduces the llc invocations from 8 to 1, and 2011-07-02 21:34:52 +00:00
thumb2-and2.ll
thumb2-and.ll
thumb2-asr2.ll
thumb2-asr.ll
thumb2-barrier.ll
thumb2-bcc.ll Introduce MCCodeGenInfo, which keeps information that can affect codegen 2011-07-19 06:37:02 +00:00
thumb2-bfc.ll
thumb2-bic.ll
thumb2-branch.ll Improve test cases from r134746. 2011-07-12 16:06:01 +00:00
thumb2-call-tc.ll
thumb2-call.ll
thumb2-cbnz.ll Since I can't reproduce the failures from 131261, re-trying with a 2011-05-13 00:51:54 +00:00
thumb2-clz.ll Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 2011-07-07 03:55:05 +00:00
thumb2-cmn2.ll
thumb2-cmn.ll Explicitly request physreg coalesing for a bunch of Thumb2 unit tests. 2011-05-04 19:02:07 +00:00
thumb2-cmp2.ll Explicitly request physreg coalesing for a bunch of Thumb2 unit tests. 2011-05-04 19:02:07 +00:00
thumb2-cmp.ll Explicitly request physreg coalesing for a bunch of Thumb2 unit tests. 2011-05-04 19:02:07 +00:00
thumb2-eor2.ll
thumb2-eor.ll
thumb2-ifcvt1-tc.ll
thumb2-ifcvt1.ll Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 2011-08-03 22:34:43 +00:00
thumb2-ifcvt2.ll
thumb2-ifcvt3.ll Last round of fixes for movw + movt global address codegen. 2011-01-21 18:55:51 +00:00
thumb2-jtb.ll
thumb2-ldm.ll Thumb assembly parsing and encoding for LDM instruction. 2011-08-18 21:50:53 +00:00
thumb2-ldr_ext.ll
thumb2-ldr_post.ll
thumb2-ldr_pre.ll
thumb2-ldr.ll
thumb2-ldrb.ll
thumb2-ldrd.ll Fix Thumb and Thumb2 tests to be register allocator independent. 2011-03-31 23:31:50 +00:00
thumb2-ldrh.ll
thumb2-lsl2.ll
thumb2-lsl.ll
thumb2-lsr2.ll
thumb2-lsr3.ll Make tests more useful. 2011-04-25 10:12:01 +00:00
thumb2-lsr.ll
thumb2-mla.ll
thumb2-mls.ll Update tests. 2011-08-19 22:19:48 +00:00
thumb2-mov.ll
thumb2-mul.ll Update tests. 2011-08-19 22:19:48 +00:00
thumb2-mulhi.ll ARMv7M vs. ARMv7E-M support. 2011-07-01 21:12:19 +00:00
thumb2-mvn2.ll
thumb2-mvn.ll
thumb2-neg.ll
thumb2-orn2.ll
thumb2-orn.ll
thumb2-orr2.ll
thumb2-orr.ll
thumb2-pack.ll
thumb2-rev16.ll
thumb2-rev.ll Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 2011-07-07 03:55:05 +00:00
thumb2-ror.ll Teach Thumb2 isel to fold and->rotr ==> ROR. 2011-04-29 14:18:15 +00:00
thumb2-rsb2.ll
thumb2-rsb.ll
thumb2-sbc.ll Don't depend on the optimization reverted in r134067. 2011-06-29 14:07:18 +00:00
thumb2-select_xform.ll
thumb2-select.ll
thumb2-shifter.ll
thumb2-smla.ll ARMv7M vs. ARMv7E-M support. 2011-07-01 21:12:19 +00:00
thumb2-smul.ll ARMv7M vs. ARMv7E-M support. 2011-07-01 21:12:19 +00:00
thumb2-spill-q.ll
thumb2-str_post.ll
thumb2-str_pre.ll
thumb2-str.ll
thumb2-strb.ll
thumb2-strh.ll
thumb2-sub2.ll
thumb2-sub3.ll Thumb2 and ARM add/subtract with carry fixes. 2011-04-23 03:55:32 +00:00
thumb2-sub4.ll
thumb2-sub5.ll Thumb2 and ARM add/subtract with carry fixes. 2011-04-23 03:55:32 +00:00
thumb2-sub.ll
thumb2-sxt_rot.ll manually upgrade a bunch of tests to modern syntax, and remove some that 2011-06-17 03:14:27 +00:00
thumb2-sxt-uxt.ll Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 2011-08-08 19:49:37 +00:00
thumb2-tbb.ll
thumb2-tbh.ll
thumb2-teq2.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-teq.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-tst2.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-tst.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-uxt_rot.ll manually upgrade a bunch of tests to modern syntax, and remove some that 2011-06-17 03:14:27 +00:00
thumb2-uxtb.ll Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. 2011-04-13 00:38:32 +00:00
tls1.ll
tls2.ll